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AGESA: Disable PCI_CFG_EXT_IO 

We don't need to do explicit pci_io_read/write operations,
as we can use MMCONF everywhere. AGESA code still enables
extended cf8/cfc should it be required by payload or OS.

Change-Id: I278e5e26eb9a247f67927cbc67e04f081ca50f7b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17535
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-20 17:31:58 +02:00
parent 59e0334207
commit b995f436b3
13 changed files with 0 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/amd/agesa/family10/Kconfig
View File

@ -16,7 +16,6 @@
config CPU_AMD_AGESA_FAMILY10
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS

1
src/cpu/amd/agesa/family12/Kconfig
View File

@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY12
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS

7
src/cpu/amd/agesa/family12/fixme.c
View File

@ -76,13 +76,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Enable Non-Post Memory in CPU */
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
PciData = (PciData >> 8) & ~0xff;

1
src/cpu/amd/agesa/family14/Kconfig
View File

@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY14
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS

7
src/cpu/amd/agesa/family14/fixme.c
View File

@ -78,13 +78,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
PciData = 0x01308002;

1
src/cpu/amd/agesa/family15/Kconfig
View File

@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY15
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS

7
src/cpu/amd/agesa/family15/fixme.c
View File

@ -269,13 +269,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | (1ULL << 46);
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
UINT32 PciData;
PCI_ADDR PciAddress;

1
src/cpu/amd/agesa/family15rl/Kconfig
View File

@ -16,7 +16,6 @@
config CPU_AMD_AGESA_FAMILY15_RL
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS

7
src/cpu/amd/agesa/family15rl/fixme.c
View File

@ -72,13 +72,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

1
src/cpu/amd/agesa/family15tn/Kconfig
View File

@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY15_TN
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS

7
src/cpu/amd/agesa/family15tn/fixme.c
View File

@ -72,13 +72,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

1
src/cpu/amd/agesa/family16kb/Kconfig
View File

@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY16_KB
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS

7
src/cpu/amd/agesa/family16kb/fixme.c
View File

@ -72,13 +72,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);