AGESA: Disable PCI_CFG_EXT_IO
We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be required by payload or OS. Change-Id: I278e5e26eb9a247f67927cbc67e04f081ca50f7b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -16,7 +16,6 @@
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config CPU_AMD_AGESA_FAMILY10
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bool
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select CPU_AMD_MODEL_10XXX
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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@ -15,7 +15,6 @@
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config CPU_AMD_AGESA_FAMILY12
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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@ -76,13 +76,6 @@ void amd_initmmio(void)
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000ull;
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LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
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/* Enable Non-Post Memory in CPU */
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PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
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PciData = (PciData >> 8) & ~0xff;
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@ -15,7 +15,6 @@
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config CPU_AMD_AGESA_FAMILY14
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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@ -78,13 +78,6 @@ void amd_initmmio(void)
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000ull;
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LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
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/* Set Ontario Link Data */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
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PciData = 0x01308002;
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@ -15,7 +15,6 @@
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config CPU_AMD_AGESA_FAMILY15
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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@ -269,13 +269,6 @@ void amd_initmmio(void)
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
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/*
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* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | (1ULL << 46);
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LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
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#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
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UINT32 PciData;
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PCI_ADDR PciAddress;
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@ -16,7 +16,6 @@
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config CPU_AMD_AGESA_FAMILY15_RL
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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@ -72,13 +72,6 @@ void amd_initmmio(void)
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000;
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LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
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LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
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@ -15,7 +15,6 @@
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config CPU_AMD_AGESA_FAMILY15_TN
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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@ -72,13 +72,6 @@ void amd_initmmio(void)
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000;
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LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
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LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
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@ -15,7 +15,6 @@
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config CPU_AMD_AGESA_FAMILY16_KB
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bool
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select PCI_IO_CFG_EXT
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select MMCONF_SUPPORT_DEFAULT
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select X86_AMD_FIXED_MTRRS
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@ -72,13 +72,6 @@ void amd_initmmio(void)
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000;
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LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
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LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
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