soc/amd/cezanne: add verstage files
Add support for psp_verstage compilation. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kangheui Won
Martin Roth
parent
d8928e438b
commit
b997b0a04e
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@ -5,6 +5,8 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
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# Beware that all-y also adds the compilation unit to verstage on PSP
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all-y += config.c
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all-y += aoac.c
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@ -130,6 +132,18 @@ PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | a
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APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h)
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APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h)
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ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
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# type = 0x6B - PSP Shared memory location
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ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0)
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PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE)
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PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map)
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endif
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# type = 0x52 - PSP Bootloader Userspace Application (verstage)
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PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
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PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
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endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
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# Helper function to return a value with given bit set
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# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions.
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set-bit=$(call int-shift-left, 1 $(call _toint,$1))
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@ -143,6 +157,9 @@ PSP_SOFTFUSE=$(shell A=$(call int-add, \
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add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
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OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage)
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OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig)
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OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
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$(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
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$(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
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@ -152,6 +169,8 @@ OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
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OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
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OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
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OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem)
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OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size)
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OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size)
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OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base)
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OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
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@ -178,6 +197,8 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
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--combo-capable \
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$(OPT_TOKEN_UNLOCK) \
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$(OPT_WHITELIST_FILE) \
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$(OPT_PSP_SHAREDMEM_BASE) \
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$(OPT_PSP_SHAREDMEM_SIZE) \
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$(OPT_EFS_SPI_READ_MODE) \
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$(OPT_EFS_SPI_SPEED) \
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$(OPT_EFS_SPI_MICRON_FLAG) \
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@ -186,10 +207,13 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
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--flashsize $(CONFIG_ROM_SIZE)
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$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
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$(PSP_VERSTAGE_FILE) \
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$(PSP_VERSTAGE_SIG_FILE) \
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$$(PSP_APCB_FILES) \
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$(DEP_FILES) \
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$(AMDFWTOOL) \
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$(obj)/fmap_config.h
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$(obj)/fmap_config.h \
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$(objcbfs)/bootblock.elf # this target also creates the .map file
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$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
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rm -f $@
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@printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
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@ -197,6 +221,8 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
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$(AMDFW_COMMON_ARGS) \
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$(OPT_APOB_NV_SIZE) \
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$(OPT_APOB_NV_BASE) \
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$(OPT_VERSTAGE_FILE) \
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$(OPT_VERSTAGE_SIG_FILE) \
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--location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \
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--multilevel \
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--output $@
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_CEZANNE_PSP_VERSTAGE_ADDR_H
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#define AMD_CEZANNE_PSP_VERSTAGE_ADDR_H
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/*
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* Start of available space is 0x36000 and this is where the
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* header for the user app (verstage) must be mapped.
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* Size is 0x14000 bytes
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*/
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#define PSP_SRAM_START 0x36000
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#define PSP_SRAM_SIZE (80K)
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#define VERSTAGE_START PSP_SRAM_START
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/*
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* The top of the stack must be 4k aligned, so set the bottom as 4k aligned
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* and make the size a multiple of 4k
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*/
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#define PSP_VERSTAGE_STACK_START 0x49000
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#define PSP_VERSTAGE_STACK_SIZE (4K)
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#endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */
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@ -0,0 +1,17 @@
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# SPDX-License-Identifier: GPL-2.0-only
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verstage-generic-ccopts += -I$(src)/soc/amd/cezanne/psp_verstage/include
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verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include
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verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
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subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
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verstage-y += svc.c
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verstage-y += stub.c
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verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S
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verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S
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$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf
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$(OBJCOPY_verstage) -O binary $^ $@
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@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file contains stub for not-yet-implemented svc in cezanne PSP.
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* So this file will and should be removed eventually when psp_verstage works
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* correctly in cezanne.
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*/
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#include <bl_uapp/bl_syscall_public.h>
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#include <console/console.h>
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#include <psp_verstage.h>
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#include <reset.h>
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#include <timer.h>
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uint32_t svc_write_postcode(uint32_t postcode)
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{
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return 0;
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}
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static uint64_t tmp_timer_value = 0;
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void timer_monotonic_get(struct mono_time *mt)
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{
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mt->microseconds = tmp_timer_value / 1000;
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tmp_timer_value++;
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}
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void do_board_reset(void)
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{
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printk(BIOS_ERR, "Reset not implemented yet.\n");
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while (1)
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;
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}
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@ -0,0 +1,109 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include "svc.h"
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#include <assert.h>
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#include <bl_uapp/bl_syscall_public.h>
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#include <psp_verstage.h>
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#include <stddef.h>
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void svc_exit(uint32_t status)
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{
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uint32_t unused = 0;
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SVC_CALL0(SVC_EXIT, unused);
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}
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void svc_debug_print(const char *string)
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{
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uint32_t unused = 0;
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SVC_CALL1(SVC_DEBUG_PRINT, (uint32_t)string, unused);
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}
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void svc_debug_print_ex(uint32_t dword0,
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uint32_t dword1, uint32_t dword2, uint32_t dword3)
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{
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uint32_t unused = 0;
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SVC_CALL4(SVC_DEBUG_PRINT_EX, dword0, dword1, dword2, dword3, unused);
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}
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uint32_t svc_get_boot_mode(uint32_t *boot_mode)
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{
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uint32_t retval = 0;
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SVC_CALL1(SVC_GET_BOOT_MODE, boot_mode, retval);
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return retval;
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}
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void svc_delay_in_usec(uint32_t delay)
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{
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uint32_t i;
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for (i = 0; i < delay * 1000; i++)
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asm volatile ("nop");
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}
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uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info)
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{
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uint32_t retval = 0;
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SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval);
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return retval;
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}
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uint32_t svc_map_fch_dev(enum fch_io_device io_device,
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uint32_t arg1, uint32_t arg2, void **io_device_axi_addr)
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{
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uint32_t retval = 0;
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assert(io_device < FCH_IO_DEVICE_END);
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SVC_CALL4(SVC_MAP_FCH_IO_DEVICE, io_device, arg1, arg2,
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(uint32_t)io_device_axi_addr, retval);
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return retval;
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}
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uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr)
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{
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uint32_t retval = 0;
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assert(io_device < FCH_IO_DEVICE_END);
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SVC_CALL2(SVC_UNMAP_FCH_IO_DEVICE, (uint32_t)io_device,
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(uint32_t)io_device_axi_addr, retval);
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return retval;
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}
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uint32_t svc_map_spi_rom(void *spi_rom_addr,
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uint32_t size, void **spi_rom_axi_addr)
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{
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uint32_t retval = 0;
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SVC_CALL3(SVC_MAP_SPIROM_DEVICE, spi_rom_addr, size,
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(uint32_t)spi_rom_axi_addr, retval);
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return retval;
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}
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uint32_t svc_unmap_spi_rom(void *spi_rom_addr)
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{
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uint32_t retval = 0;
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SVC_CALL1(SVC_UNMAP_SPIROM_DEVICE, (uint32_t)spi_rom_addr, retval);
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return retval;
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}
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uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset)
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{
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return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset);
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}
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uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset,
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uint32_t *bios_dir_offset)
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{
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uint32_t retval = 0;
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SVC_CALL2(SVC_UPDATE_PSP_BIOS_DIR, (uint32_t)psp_dir_offset,
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(uint32_t)bios_dir_offset, retval);
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return retval;
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}
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uint32_t save_uapp_data(void *address, uint32_t size)
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{
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return svc_save_uapp_data(address, size);
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}
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uint32_t svc_save_uapp_data(void *address, uint32_t size)
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{
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uint32_t retval = 0;
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SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval);
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return retval;
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}
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@ -0,0 +1,57 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef PSP_VERSTAGE_SVC_H
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#define PSP_VERSTAGE_SVC_H
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#define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \
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__asm__ __volatile__ ( \
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"mov r0, %[reg0]\n\t" \
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"mov r1, %[reg1]\n\t" \
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"mov r2, %[reg2]\n\t" \
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"mov r3, %[reg3]\n\t" \
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"svc %[id]\n\t" \
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"mov %[result], r0\n\t" \
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: [result] "=r" (Ret) /* output */ \
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: [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2), \
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[reg3] "r" (R3) /* input(s) */ \
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: "r0", "r1", "r2", "r3", "memory", "cc" /* list of clobbered registers */)
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#define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \
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__asm__ __volatile__ ( \
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"mov r0, %[reg0]\n\t" \
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"mov r1, %[reg1]\n\t" \
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"mov r2, %[reg2]\n\t" \
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"svc %[id]\n\t" \
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"mov %[result], r0\n\t" \
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: [result] "=r" (Ret) /* output */ \
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: [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2) \
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: "r0", "r1", "r2", "memory", "cc" /* list of clobbered registers */)
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#define SVC_CALL2(SVC_ID, R0, R1, Ret) \
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__asm__ __volatile__ ( \
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"mov r0, %[reg0]\n\t" \
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"mov r1, %[reg1]\n\t" \
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"svc %[id]\n\t" \
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"mov %[result], r0\n\t" \
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: [result] "=r" (Ret) /* output */ \
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: [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1)/* input(s) */ \
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: "r0", "r1", "memory", "cc" /* list of clobbered registers */)
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#define SVC_CALL1(SVC_ID, R0, Ret) \
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__asm__ __volatile__ ( \
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"mov r0, %[reg0]\n\t" \
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"svc %[id]\n\t" \
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"mov %[result], r0\n\t" \
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: [result] "=r" (Ret) /* output */ \
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: [id] "i" (SVC_ID), [reg0] "r" (R0) /* input(s) */ \
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: "r0", "memory", "cc" /* list of clobbered registers */)
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#define SVC_CALL0(SVC_ID, Ret) \
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__asm__ __volatile__ ( \
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"svc %[id]\n\t" \
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"mov %[result], r0\n\t" \
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: [result] "=r" (Ret) /* output */ \
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: [id] "I" (SVC_ID) /* input(s) */ \
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: "memory", "cc" /* list of clobbered registers */)
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#endif /* PSP_VERSTAGE_SVC_H */
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@ -1,7 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
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verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include
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verstage-generic-ccopts += -D__USER_SPACE__
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CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/
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