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sc7180: Remove the delay to force hpd detection and always disable HPD 

HPD on this bridge chip is a bit useless. This is an eDP bridge so the HPD is
an internal signal that's only there to signal that the panel is done powering up.
But the bridge chip debounces this signal by between 100 ms and 400 ms (depending on process,
voltage, and temperate). One particular panel asserted HPD 84 ms after it was powered on
meaning that we saw HPD 284 ms after power on. Assume that the panel driver will have the
hardcoded delay in its prepare and always disable HPD.

Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Vinod Polimera 2020-09-21 08:55:16 +05:30 committed by Julius Werner
parent 3c667a2e7d
commit b9a7d779b3
1 changed files with 2 additions and 30 deletions
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32
src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
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@ -431,35 +431,6 @@ static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip)
printk(BIOS_ERR, "ERROR: Link training failed 10 times\n");
}
static enum cb_err sn65dsi86_bridge_get_plug_in_status(uint8_t bus, uint8_t chip)
{
int val;
uint8_t buf;
val = i2c_readb(bus, chip, SN_HPD_DISABLE_REG, &buf);
if (val == 0 && (buf & HPD_DISABLE))
return CB_SUCCESS;
return CB_ERR;
}
/*
* support bridge HPD function some hardware versions do not support bridge hdp,
* we use 360ms to try to get the hpd single now, if we can not get bridge hpd single,
* it will delay 360ms, also meet the bridge power timing request, to be compatible
* all of the hardware versions
*/
static void sn65dsi86_bridge_wait_hpd(uint8_t bus, uint8_t chip)
{
if (wait_ms(400, sn65dsi86_bridge_get_plug_in_status(bus, chip)))
return;
printk(BIOS_WARNING, "HPD detection failed, force hpd\n");
/* Force HPD */
i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0);
}
static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable)
{
if (enable)
@ -481,7 +452,8 @@ static int sn65dsi86_bridge_dp_lane_config(uint8_t bus, uint8_t chip)
void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk)
{
sn65dsi86_bridge_wait_hpd(bus, chip);
/* disable HPD */
i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0);
/* set refclk to 19.2 MHZ */
i2c_write_field(bus, chip, SN_DPPLL_SRC_REG, ref_clk, 7, 1);