haswell: use #defines for constants in udelay.c
Change the hard coded values in udelay.c to use the #defines for MSRs and BCLK. Change-Id: I2bbeb0b478d2e3ca155e8f82006df86c29a4f018 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2629 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -21,10 +21,7 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include "cpu/intel/haswell/haswell.h"
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/**
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* Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
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*/
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/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
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/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
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static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
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static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
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@ -42,13 +39,13 @@ void udelay(u32 us)
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u32 dword;
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u32 dword;
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tsc_t tsc, tsc1, tscd;
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tsc_t tsc, tsc1, tscd;
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msr_t msr;
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msr_t msr;
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u32 fsb = 100, divisor;
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u32 divisor;
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u32 d; /* ticks per us */
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u32 d; /* ticks per us */
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msr = rdmsr(0xce);
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msr = rdmsr(MSR_PLATFORM_INFO);
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divisor = (msr.lo >> 8) & 0xff;
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divisor = (msr.lo >> 8) & 0xff;
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d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
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d = HASWELL_BCLK * divisor;
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multiply_to_tsc(&tscd, us, d);
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multiply_to_tsc(&tscd, us, d);
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tsc1 = rdtsc();
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tsc1 = rdtsc();
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