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cosmetics. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-20 15:49:59 +00:00 committed by Stefan Reinauer
parent 169dc7e5ac
commit b9aea8933c
2 changed files with 9 additions and 16 deletions
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18
src/northbridge/amd/lx/pll_reset.c
View File

@ -24,17 +24,13 @@ static void pll_reset(char manualconf)
msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
print_debug("_MSR GLCP_SYS_RSTPLL (");
print_debug_hex32(GLCP_SYS_RSTPLL);
print_debug(") value is: ");
print_debug_hex32(msrGlcpSysRstpll.hi);
print_debug(":");
print_debug_hex32(msrGlcpSysRstpll.lo);
print_debug("\n");
printk(BIOS_DEBUG, "MSR GLCP_SYS_RSTPLL (%08x) value is %08x:%08x\n",
GLCP_SYS_RSTPLL, msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
post_code(POST_PLL_INIT);
if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
print_debug("Configuring PLL\n");
printk(BIOS_DEBUG, "Configuring PLL.\n");
if (manualconf) {
post_code(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
@ -62,13 +58,13 @@ static void pll_reset(char manualconf)
msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* You should never get here..... The chip has reset. */
print_debug("CONFIGURING PLL FAILURE\n");
/* You should never get here..... The chip has reset. */
printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n");
post_code(POST_PLL_RESET_FAIL);
__asm__ __volatile__("hlt\n");
}
print_debug("Done pll_reset\n");
printk(BIOS_DEBUG, "PLL configured.\n");
return;
}

7
src/northbridge/amd/lx/raminit.c
View File

@ -29,10 +29,7 @@ static const unsigned char NumColAddr[] = {
static void banner(const char *s)
{
/* This is so ugly. */
print_debug("===========================");
print_debug(s);
print_debug("======================================\n");
printk(BIOS_DEBUG, " * %s\n", s);
}
static void hcf(void)
@ -572,7 +569,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
uint8_t spd_byte;
banner("sdram_set_spd_register\n");
banner("sdram_set_spd_register");
post_code(POST_MEM_SETUP); // post_70h
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);