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soc/intel: Drop unused lpss functions 

This change drops the following unused lpss functions and related
code:
* soc_lpss_controllers_list
* is_dev_lpss

These functions were added to determine if a controller is LPSS for
performing IRQ configuration. But, these never got used and hence are
being dropped.

Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Furquan Shaikh 2021-06-04 06:16:36 -07:00 committed by Patrick Georgi
parent c6a3f34096
commit b9b6f4d013
8 changed files with 0 additions and 148 deletions
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23
src/soc/intel/alderlake/fsp_params.c
View File

@ -67,22 +67,6 @@ static void parse_devicetree(FSP_S_CONFIG *params)
params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
}
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
PCH_DEVFN_I2C2,
PCH_DEVFN_I2C3,
PCH_DEVFN_I2C4,
PCH_DEVFN_I2C5,
PCH_DEVFN_GSPI0,
PCH_DEVFN_GSPI1,
PCH_DEVFN_GSPI2,
PCH_DEVFN_GSPI3,
PCH_DEVFN_UART0,
PCH_DEVFN_UART1,
PCH_DEVFN_UART2
};
__weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
/* Override settings per board. */
@ -334,10 +318,3 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Return list of SOC LPSS controllers */
const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
{
*size = ARRAY_SIZE(serial_io_dev);
return serial_io_dev;
}

7
src/soc/intel/cannonlake/fsp_params.c
View File

@ -572,13 +572,6 @@ __weak void mainboard_silicon_init_params(FSPS_UPD *supd)
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Return list of SOC LPSS controllers */
const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
{
*size = ARRAY_SIZE(serial_io_dev);
return serial_io_dev;
}
/* Handle FSP logo params */
void soc_load_logo(FSPS_UPD *supd)
{

9
src/soc/intel/common/block/include/intelblocks/lpss.h
View File

@ -27,13 +27,4 @@ bool lpss_is_controller_in_reset(uintptr_t base);
/* Set controller power state to D0 or D3*/
void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state);
/*
* Handler to get list of LPSS controllers. The SOC is expected to send out a
* list of pci devfn for all LPSS controllers supported by the SOC.
*/
const pci_devfn_t *soc_lpss_controllers_list(size_t *size);
/* Check if the device is a LPSS controller */
bool is_dev_lpss(const struct device *dev);
#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */

18
src/soc/intel/common/block/lpss/lpss.c
View File

@ -72,21 +72,3 @@ void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state)
reg8 |= state;
pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8);
}
bool is_dev_lpss(const struct device *dev)
{
static size_t size;
static const pci_devfn_t *lpss_devices;
if (dev->path.type != DEVICE_PATH_PCI)
return false;
if (!lpss_devices)
lpss_devices = soc_lpss_controllers_list(&size);
for (int i = 0; i < size; i++) {
if (lpss_devices[i] == dev->path.pci.devfn)
return true;
}
return false;
}

24
src/soc/intel/elkhartlake/fsp_params.c
View File

@ -41,23 +41,6 @@ static int get_l1_substate_control(enum L1_substates_control ctl)
return ctl - 1;
}
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
PCH_DEVFN_I2C2,
PCH_DEVFN_I2C3,
PCH_DEVFN_I2C4,
PCH_DEVFN_I2C5,
PCH_DEVFN_I2C6,
PCH_DEVFN_I2C7,
PCH_DEVFN_GSPI0,
PCH_DEVFN_GSPI1,
PCH_DEVFN_GSPI2,
PCH_DEVFN_UART0,
PCH_DEVFN_UART1,
PCH_DEVFN_UART2
};
static void parse_devicetree(FSP_S_CONFIG *params)
{
const struct soc_intel_elkhartlake_config *config = config_of_soc();
@ -287,10 +270,3 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Return list of SOC LPSS controllers */
const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
{
*size = ARRAY_SIZE(serial_io_dev);
return serial_io_dev;
}

22
src/soc/intel/icelake/fsp_params.c
View File

@ -33,21 +33,6 @@ static void parse_devicetree(FSP_S_CONFIG *params)
params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
}
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
PCH_DEVFN_I2C2,
PCH_DEVFN_I2C3,
PCH_DEVFN_I2C4,
PCH_DEVFN_I2C5,
PCH_DEVFN_GSPI0,
PCH_DEVFN_GSPI1,
PCH_DEVFN_GSPI2,
PCH_DEVFN_UART0,
PCH_DEVFN_UART1,
PCH_DEVFN_UART2
};
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
@ -223,10 +208,3 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Return list of SOC LPSS controllers */
const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
{
*size = ARRAY_SIZE(serial_io_dev);
return serial_io_dev;
}

22
src/soc/intel/jasperlake/fsp_params.c
View File

@ -28,21 +28,6 @@ enum {
EOP_DXE,
} EndOfPost;
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
PCH_DEVFN_I2C2,
PCH_DEVFN_I2C3,
PCH_DEVFN_I2C4,
PCH_DEVFN_I2C5,
PCH_DEVFN_GSPI0,
PCH_DEVFN_GSPI1,
PCH_DEVFN_GSPI2,
PCH_DEVFN_UART0,
PCH_DEVFN_UART1,
PCH_DEVFN_UART2
};
static void parse_devicetree(FSP_S_CONFIG *params)
{
const struct soc_intel_jasperlake_config *config = config_of_soc();
@ -266,10 +251,3 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Return list of SOC LPSS controllers */
const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
{
*size = ARRAY_SIZE(serial_io_dev);
return serial_io_dev;
}

23
src/soc/intel/tigerlake/fsp_params.c
View File

@ -132,22 +132,6 @@ static void parse_devicetree(FSP_S_CONFIG *params)
params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
}
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
PCH_DEVFN_I2C2,
PCH_DEVFN_I2C3,
PCH_DEVFN_I2C4,
PCH_DEVFN_I2C5,
PCH_DEVFN_GSPI0,
PCH_DEVFN_GSPI1,
PCH_DEVFN_GSPI2,
PCH_DEVFN_GSPI3,
PCH_DEVFN_UART0,
PCH_DEVFN_UART1,
PCH_DEVFN_UART2
};
__weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config)
{
/* Override settings per board. */
@ -483,10 +467,3 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Return list of SOC LPSS controllers */
const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
{
*size = ARRAY_SIZE(serial_io_dev);
return serial_io_dev;
}