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northbridge/intel/haswell: Fix undefined behavior 

Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.

Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Ryan Salsamendi 2017-07-04 13:35:06 -07:00 committed by Nico Huber
parent 70c27de571
commit b9bc2571be
3 changed files with 11 additions and 7 deletions
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10
src/northbridge/intel/haswell/acpi.c
View File

@ -29,6 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
u32 pciexbar = 0; u32 pciexbar = 0;
u32 pciexbar_reg; u32 pciexbar_reg;
int max_buses; int max_buses;
u32 mask;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev) if (!dev)
@ -40,17 +41,20 @@ unsigned long acpi_fill_mcfg(unsigned long current)
if (!(pciexbar_reg & (1 << 0))) if (!(pciexbar_reg & (1 << 0)))
return current; return current;
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
switch ((pciexbar_reg >> 1) & 3) { switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB case 0: // 256MB
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); pciexbar = pciexbar_reg & mask;
max_buses = 256; max_buses = 256;
break; break;
case 1: // 128M case 1: // 128M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); mask |= (1 << 27);
pciexbar = pciexbar_reg & mask;
max_buses = 128; max_buses = 128;
break; break;
case 2: // 64M case 2: // 64M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); mask |= (1 << 27) | (1 << 26);
pciexbar = pciexbar_reg & mask;
max_buses = 64; max_buses = 64;
break; break;
default: // RSVD default: // RSVD

2
src/northbridge/intel/haswell/early_init.c
View File

@ -81,7 +81,7 @@ static void haswell_setup_graphics(void)
/* GPU RC6 workaround for sighting 366252 */ /* GPU RC6 workaround for sighting 366252 */
reg32 = MCHBAR32(0x5d14); reg32 = MCHBAR32(0x5d14);
reg32 |= (1 << 31); reg32 |= (1UL << 31);
MCHBAR32(0x5d14) = reg32; MCHBAR32(0x5d14) = reg32;
/* VLW */ /* VLW */

6
src/northbridge/intel/haswell/finalize.c
View File

@ -35,11 +35,11 @@ void intel_northbridge_haswell_finalize_smm(void)
pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */ pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ MCHBAR32_OR(0x5f00, 1UL << 31); /* SA PM */
MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
MCHBAR32_OR(0x6800, 1 << 31); MCHBAR32_OR(0x6800, 1UL << 31);
MCHBAR32_OR(0x7000, 1 << 31); MCHBAR32_OR(0x7000, 1UL << 31);
MCHBAR32_OR(0x77fc, 1 << 0); MCHBAR32_OR(0x77fc, 1 << 0);
/* Memory Controller Lockdown */ /* Memory Controller Lockdown */