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sb/intel/i82371eb: Consolidate bootblock.c logic 

The southbridge bootblock entry point bootblock_southbridge_init()
just calls i82371eb_enable_rom() which does all the work. Move all
that code into bootblock_southbridge_init() and drop the second
function.

Plus combine the 3 lines that set 3 bits in XBCS into one.

Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Keith Hui 2017-09-04 15:47:40 -04:00 committed by Martin Roth
parent 427feecbf0
commit b9c1a4e8d9
1 changed files with 2 additions and 9 deletions
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11
src/southbridge/intel/i82371eb/bootblock.c
View File

@ -19,7 +19,7 @@
#include <device/pci_ids.h>
#include "i82371eb.h"
static void i82371eb_enable_rom(void)
static void bootblock_southbridge_init(void)
{
u16 reg16;
pci_devfn_t dev;
@ -36,14 +36,7 @@ static void i82371eb_enable_rom(void)
/* Enable access to the whole ROM, disable ROM write access. */
reg16 = pci_read_config16(dev, XBCS);
reg16 |= LOWER_BIOS_ENABLE;
reg16 |= EXT_BIOS_ENABLE;
reg16 |= EXT_BIOS_ENABLE_1MB;
reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB;
reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
pci_write_config16(dev, XBCS, reg16);
}
static void bootblock_southbridge_init(void)
{
i82371eb_enable_rom();
}