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mediatek/mt8183: Calibrate RTC eosc clock 

Calibrate RTC eosc clock which will be used when RTC goes into
low power state.

BUG=b:133872611
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ie8fd6f4cffdcf7cf410ce48343378a017923789c
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Ran Bi 2019-06-30 10:46:30 +08:00 committed by Martin Roth
parent a9ee8fcbb0
commit b9cc7b38f8
2 changed files with 196 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
src/soc/mediatek/mt8183/include/soc/rtc.h
View File

@ -128,6 +128,9 @@ enum {
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
@ -136,6 +139,11 @@ enum {
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
};
enum {
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
PMIC_RG_FQMTR_CK_PDN_SHIFT = 11
};
/* PMIC DCXO Register Definition */
enum {
PMIC_RG_DCXO_CW00 = 0x0788,
@ -155,6 +163,56 @@ enum {
PMIC_RG_TOP_TMA_KEY = 0x03A8
};
/* PMIC Frequency Meter Definition */
enum {
PMIC_RG_FQMTR_CKSEL = 0x0118,
PMIC_RG_FQMTR_RST = 0x013E,
PMIC_RG_FQMTR_CON0 = 0x0514,
PMIC_RG_FQMTR_WINSET = 0x0516,
PMIC_RG_FQMTR_DATA = 0x0518,
FQMTR_TIMEOUT_US = 8000
};
enum {
PMIC_FQMTR_FIX_CLK_26M = 0U << 0,
PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0,
PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0,
PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0,
PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U << 0,
PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0,
PMIC_FQMTR_FIX_CLK_PMU_75K = 6U << 0,
PMIC_FQMTR_CKSEL_MASK = 7U << 0
};
enum {
PMIC_FQMTR_RST_SHIFT = 8
};
enum {
PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
PMIC_FQMTR_CON0_BUSY = 1U << 3,
PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15
};
enum {
RTC_FQMTR_LOW_BASE = 794 - 2,
RTC_FQMTR_HIGH_BASE = 794 + 2
};
enum {
RTC_XOSCCALI_START = 0x00,
RTC_XOSCCALI_END = 0x1f
};
/* external API */
void rtc_bbpu_power_on(void);
void rtc_osc_init(void);

139
src/soc/mediatek/mt8183/rtc.c
View File

@ -19,6 +19,7 @@
#include <soc/rtc.h>
#include <soc/mt6358.h>
#include <soc/pmic_wrap.h>
#include <timer.h>
#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8))
@ -79,11 +80,145 @@ static int rtc_gpio_init(void)
return rtc_write_trigger();
}
/* set xosc mode */
static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
{
u16 bbpu, osc32con;
u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
struct stopwatch sw;
if (val) {
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_read(RTC_OSC32CON, &osc32con);
rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
(val & RTC_XOSCCALI_MASK));
}
/* enable FQMTR clock */
pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
PMIC_RG_FQMTR_CK_PDN_SHIFT);
/* FQMTR reset */
pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT);
do {
rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
} while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY));
rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst);
/* FQMTR normal */
pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT);
/* set frequency meter window value (0=1X32K(fixed clock)) */
rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
/* enable 26M and set test clock source */
rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
/* enable 26M -> delay 100us -> enable FQMTR */
udelay(100);
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
/* enable FQMTR */
rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
udelay(100);
stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US);
/* FQMTR read until ready */
do {
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
if (stopwatch_expired(&sw)) {
rtc_info("get frequency time out !!\n");
return 0;
}
} while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);
/* read data should be closed to 26M/32k = 794 */
rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
/* disable FQMTR */
rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
/* disable FQMTR -> delay 100us -> disable 26M */
udelay(100);
/* disable 26M */
rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
rtc_write(PMIC_RG_FQMTR_CON0,
fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
rtc_info("input=0x%x, output=%d\n", val, fqmtr_data);
/* disable FQMTR clock */
pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
PMIC_RG_FQMTR_CK_PDN_SHIFT);
return fqmtr_data;
}
/* 32k clock calibration */
static u16 rtc_eosc_cali(void)
{
u16 middle, diff1, diff2, cksel;
u16 val = 0;
u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END;
rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
cksel &= ~PMIC_FQMTR_CKSEL_MASK;
/* select EOSC_32 as fixed clock */
rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K);
rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel);
while (left <= right) {
middle = (right + left) / 2;
if (middle == left)
break;
/* select 26M as target clock */
val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0);
if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE))
break;
if (val > RTC_FQMTR_HIGH_BASE)
right = middle;
else
left = middle;
}
if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE))
return middle;
val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0);
if (val > RTC_FQMTR_LOW_BASE)
diff1 = val - RTC_FQMTR_LOW_BASE;
else
diff1 = RTC_FQMTR_LOW_BASE - val;
val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0);
if (val > RTC_FQMTR_LOW_BASE)
diff2 = val - RTC_FQMTR_LOW_BASE;
else
diff2 = RTC_FQMTR_LOW_BASE - val;
if (diff1 < diff2)
return left;
else
return right;
}
void rtc_osc_init(void)
{
u16 osc32con;
/* enable 32K export */
rtc_gpio_init();
/* Calibrate eosc32 for powerdown clock */
rtc_read(RTC_OSC32CON, &osc32con);
osc32con &= ~RTC_XOSCCALI_MASK;
osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK;
rtc_xosc_write(osc32con);
rtc_info("EOSC32 cali val = 0x%x\n", osc32con);
}
/* enable lpd subroutine */
@ -196,6 +331,8 @@ int rtc_init(u8 recover)
goto err;
}
rtc_osc_init();
if (recover)
mdelay(20);