src/soc/intel/common/block/cse: Make hfsts1 common & add helper functions
Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs, hence move it to common. Also add below helper function, * wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE". It's a special CSE mode, the mode ensures CSE does not trigger any spi cycles to CSE region. * set_host_ready() - Clears reset state from host CSR. TEST=Verified CSE recover mode on CML RVP & Hatch board Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
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@ -32,30 +32,6 @@ enum {
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ME_WSTATE_NORMAL = 0x05,
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};
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/* Host Firmware Status Register 1 */
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union hfsts1 {
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uint32_t raw;
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struct {
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uint32_t working_state : 4;
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uint32_t mfg_mode : 1;
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uint32_t fpt_bad : 1;
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uint32_t operation_state : 3;
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uint32_t fw_init_complete : 1;
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uint32_t ft_bup_ld_flr : 1;
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uint32_t fw_upd_in_progress : 1;
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uint32_t error_code : 4;
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uint32_t operation_mode : 4;
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uint32_t reset_count : 4;
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uint32_t boot_options : 1;
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uint32_t rsvd0 : 1;
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uint32_t bist_state : 1;
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uint32_t bist_reset_req : 1;
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uint32_t power_source : 2;
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uint32_t reserved1 : 1;
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uint32_t d0i3_support_valid : 1;
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} __packed fields;
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};
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/* Host Firmware Status Register 2 */
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union hfsts2 {
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uint32_t raw;
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@ -174,7 +150,7 @@ static void print_me_version(void *unused)
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struct version fitc;
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} __packed;
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union hfsts1 hfsts1;
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union me_hfsts1 hfsts1;
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const struct mkhi_hdr fw_ver_msg = {
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.group_id = MKHI_GEN_GROUP_ID,
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.command = MKHI_GET_FW_VERSION,
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@ -189,7 +165,7 @@ static void print_me_version(void *unused)
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if (!is_cse_enabled())
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return;
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hfsts1.raw = me_read_config32(PCI_ME_HFSTS1);
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hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
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/*
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* Prerequisites:
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@ -225,7 +201,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL);
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void dump_me_status(void *unused)
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{
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union hfsts1 hfsts1;
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union me_hfsts1 hfsts1;
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union hfsts2 hfsts2;
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union hfsts3 hfsts3;
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union hfsts4 hfsts4;
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@ -235,7 +211,7 @@ void dump_me_status(void *unused)
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if (!is_cse_enabled())
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return;
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hfsts1.raw = me_read_config32(PCI_ME_HFSTS1);
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hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
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hfsts2.raw = me_read_config32(PCI_ME_HFSTS2);
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hfsts3.raw = me_read_config32(PCI_ME_HFSTS3);
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hfsts4.raw = me_read_config32(PCI_ME_HFSTS4);
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@ -243,7 +219,7 @@ void dump_me_status(void *unused)
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hfsts6.raw = me_read_config32(PCI_ME_HFSTS6);
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printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n",
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hfsts1.raw);
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hfsts1.data);
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printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n",
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hfsts2.raw);
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printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n",
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@ -264,9 +240,9 @@ void dump_me_status(void *unused)
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printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n",
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hfsts1.fields.fw_init_complete ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n",
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hfsts1.fields.boot_options ? "YES" : "NO");
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hfsts1.fields.boot_options_present ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Update In Progress : %s\n",
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hfsts1.fields.fw_upd_in_progress ? "YES" : "NO");
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hfsts1.fields.update_in_progress ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n",
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hfsts1.fields.d0i3_support_valid ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n",
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@ -67,6 +67,7 @@
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#define MEI_HDR_CSE_ADDR_START 0
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#define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
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#define HECI_OP_MODE_SEC_OVERRIDE 5
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static struct cse_device {
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uintptr_t sec_bar;
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@ -239,6 +240,43 @@ static int cse_ready(void)
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return csr & CSR_READY;
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}
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/*
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* Checks if CSE is in SEC_OVERRIDE operation mode. This is the mode where
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* CSE will allow reflashing of CSE region.
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*/
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static uint8_t check_cse_sec_override_mode(void)
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{
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union me_hfsts1 hfs1;
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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if (hfs1.fields.operation_mode == HECI_OP_MODE_SEC_OVERRIDE)
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return 1;
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return 0;
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}
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/* Makes the host ready to communicate with CSE */
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void set_host_ready(void)
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{
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uint32_t csr;
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csr = read_host_csr();
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csr &= ~CSR_RESET;
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csr |= (CSR_IG | CSR_READY);
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write_host_csr(csr);
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}
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/* Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds */
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uint8_t wait_cse_sec_override_mode(void)
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{
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY);
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while (!check_cse_sec_override_mode()) {
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udelay(HECI_DELAY);
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if (stopwatch_expired(&sw))
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return 0;
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}
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return 1;
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}
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static int wait_heci_ready(void)
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{
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struct stopwatch sw;
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@ -484,17 +522,12 @@ int heci_reset(void)
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/* Send reset request */
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csr = read_host_csr();
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csr |= CSR_RESET;
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csr |= CSR_IG;
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csr |= (CSR_RESET | CSR_IG);
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write_host_csr(csr);
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if (wait_heci_ready()) {
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/* Device is back on its imaginary feet, clear reset */
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csr = read_host_csr();
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csr &= ~CSR_RESET;
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csr |= CSR_IG;
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csr |= CSR_READY;
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write_host_csr(csr);
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set_host_ready();
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return 1;
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}
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@ -29,6 +29,30 @@ enum {
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PCI_ME_HFSTS6 = 0x6C,
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};
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/* ME Host Firmware Status register 1 */
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union me_hfsts1 {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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u32 reserved1: 1;
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u32 bist_test_state: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 d3_support_valid: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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/* set up device for use in early boot enviroument with temp bar */
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void heci_init(uintptr_t bar);
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/*
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*/
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bool is_cse_enabled(void);
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/* Makes the host ready to communicate with CSE*/
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void set_host_ready(void);
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/*
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* Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
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* Returns 0 on failure a 1 on success.
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*/
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uint8_t wait_cse_sec_override_mode(void);
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#define BIOS_HOST_ADDR 0x00
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#define HECI_MKHI_ADDR 0x07
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@ -47,30 +47,6 @@
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#define ME_HFS_POWER_SOURCE_AC 1
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#define ME_HFS_POWER_SOURCE_DC 2
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union me_hfs {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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u32 reserved1: 1;
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u32 bist_test_state: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 d3_support_valid: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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#define PCI_ME_HFSTS2 0x48
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/* Infrastructure Progress Values */
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#define ME_HFS2_PHASE_ROM 0
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#define ME_HFS2_PHASE_UKERNEL 2
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@ -229,7 +229,7 @@ static void print_me_version(void *unused)
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struct fw_ver_resp resp;
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size_t resp_size = sizeof(resp);
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union me_hfs hfs;
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union me_hfsts1 hfs1;
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/*
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* Print ME version only if UART debugging is enabled. Else, it takes ~1
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if (!is_cse_enabled())
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return;
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hfs.data = me_read_config32(PCI_ME_HFSTS1);
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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/*
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* This command can be run only if:
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* - Working state is normal and
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* - Operation mode is normal.
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*/
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if ((hfs.fields.working_state != ME_HFS_CWS_NORMAL) ||
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(hfs.fields.operation_mode != ME_HFS_MODE_NORMAL))
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if ((hfs1.fields.working_state != ME_HFS_CWS_NORMAL) ||
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(hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL))
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goto failed;
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/*
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@ -282,7 +282,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL);
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void intel_me_status(void)
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{
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union me_hfs hfs;
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union me_hfsts1 hfs1;
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union me_hfs2 hfs2;
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union me_hfs3 hfs3;
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union me_hfs6 hfs6;
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@ -290,13 +290,13 @@ void intel_me_status(void)
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if (!is_cse_enabled())
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return;
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hfs.data = me_read_config32(PCI_ME_HFSTS1);
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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hfs2.data = me_read_config32(PCI_ME_HFSTS2);
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hfs3.data = me_read_config32(PCI_ME_HFSTS3);
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hfs6.data = me_read_config32(PCI_ME_HFSTS6);
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printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n",
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hfs.data);
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hfs1.data);
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printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n",
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hfs2.data);
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printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n",
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@ -309,21 +309,21 @@ void intel_me_status(void)
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hfs6.data);
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/* Check Current States */
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printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n",
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hfs.fields.fpt_bad ? "BAD" : "OK");
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hfs1.fields.fpt_bad ? "BAD" : "OK");
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printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n",
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hfs.fields.ft_bup_ld_flr ? "YES" : "NO");
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hfs1.fields.ft_bup_ld_flr ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n",
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hfs.fields.fw_init_complete ? "YES" : "NO");
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hfs1.fields.fw_init_complete ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n",
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hfs.fields.mfg_mode ? "YES" : "NO");
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hfs1.fields.mfg_mode ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n",
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hfs.fields.boot_options_present ? "YES" : "NO");
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hfs1.fields.boot_options_present ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Update In Progress : %s\n",
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hfs.fields.update_in_progress ? "YES" : "NO");
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hfs1.fields.update_in_progress ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: D3 Support : %s\n",
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hfs.fields.d3_support_valid ? "YES" : "NO");
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hfs1.fields.d3_support_valid ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n",
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hfs.fields.d0i3_support_valid ? "YES" : "NO");
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hfs1.fields.d0i3_support_valid ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n",
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hfs2.fields.low_power_state ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n",
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printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n",
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hfs2.fields.cpu_replaced_valid ? "YES" : "NO");
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printk(BIOS_DEBUG, "ME: Current Working State : %s\n",
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me_cws_values[hfs.fields.working_state]);
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me_cws_values[hfs1.fields.working_state]);
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printk(BIOS_DEBUG, "ME: Current Operation State : %s\n",
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me_opstate_values[hfs.fields.operation_state]);
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me_opstate_values[hfs1.fields.operation_state]);
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printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n",
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me_opmode_values[hfs.fields.operation_mode]);
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me_opmode_values[hfs1.fields.operation_mode]);
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printk(BIOS_DEBUG, "ME: Error Code : %s\n",
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me_error_values[hfs.fields.error_code]);
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me_error_values[hfs1.fields.error_code]);
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printk(BIOS_DEBUG, "ME: Progress Phase : %s\n",
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me_progress_values[hfs2.fields.progress_code]);
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printk(BIOS_DEBUG, "ME: Power Management Event : %s\n",
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int send_global_reset(void)
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{
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int status = -1;
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union me_hfs hfs;
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union me_hfsts1 hfs1;
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if (!is_cse_enabled())
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goto ret;
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/* Check ME operating mode */
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hfs.data = me_read_config32(PCI_ME_HFSTS1);
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if (hfs.fields.operation_mode)
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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if (hfs1.fields.operation_mode)
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goto ret;
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/* ME should be in Normal Mode for this command */
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