sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
parent
73ae076e95
commit
b9d2e228b6
|
@ -247,8 +247,7 @@ static void azalia_init(struct device *dev)
|
|||
pci_write_config32(dev, 0x120, reg32);
|
||||
|
||||
/* Set Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
|
||||
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
|
||||
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
|
||||
reg8 &= ~(1 << 7); // Docking not supported
|
||||
|
|
|
@ -13,12 +13,8 @@ typedef struct southbridge_intel_i82801ix_config config_t;
|
|||
|
||||
static void i82801ix_enable_device(struct device *dev)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
/* Enable SERR */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 |= PCI_COMMAND_SERR;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
|
||||
}
|
||||
|
||||
static void i82801ix_early_settings(const config_t *const info)
|
||||
|
|
|
@ -20,9 +20,7 @@ static void pci_init(struct device *dev)
|
|||
printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n");
|
||||
|
||||
/* Enable Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 |= PCI_COMMAND_MASTER;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
|
||||
/* Set Cache Line Size to 0x10 */
|
||||
// This has no effect but the OS might expect it
|
||||
|
|
|
@ -11,12 +11,8 @@
|
|||
|
||||
static void usb_ehci_init(struct device *dev)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 |= PCI_COMMAND_MASTER;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue