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urara: add support for DMA coherent memory area 

The information about the DMA memory area is further passed
through the coreboot table to the payload.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA; DMA memory area was used to test the
     functionality of the DWC2 USB controller driver; behavior was
     as expected.
BRANCH=none

Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a
Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/235910
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9593
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Ionela Voinescu 2014-12-12 13:53:22 +00:00 committed by Patrick Georgi
parent 9b99d7b435
commit b9d961550c
3 changed files with 16 additions and 2 deletions
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2
src/arch/mips/include/arch/memlayout.h
View File

@ -26,6 +26,6 @@
/* TODO: Double-check that that's the correct alignment for our ABI. */ /* TODO: Double-check that that's the correct alignment for our ABI. */
#define STACK(addr, size) REGION(stack, addr, size, 8) #define STACK(addr, size) REGION(stack, addr, size, 8)
/* TODO: Need to add DMA_COHERENT region like on ARM? */ #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K)
#endif /* __ARCH_MEMLAYOUT_H */ #endif /* __ARCH_MEMLAYOUT_H */

14
src/mainboard/google/urara/mainboard.c
View File

@ -18,9 +18,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA * MA 02110-1301 USA
*/ */
#include <arch/io.h>
#include <symbols.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <boot/coreboot_tables.h>
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)
{ {
@ -31,3 +33,13 @@ struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
}; };
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

2
src/soc/imgtec/pistachio/include/soc/memlayout.ld
View File

@ -36,4 +36,6 @@ SECTIONS
/* Let's use SRAM for CBFS cache. */ /* Let's use SRAM for CBFS cache. */
CBFS_CACHE(0x9b000000, 64K) CBFS_CACHE(0x9b000000, 64K)
/* DMA coherent area: end of available DRAM, uncached */
DMA_COHERENT(0xAFF00000, 1M)
} }