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soc/amd/cezanne/romstage: Store early dram region 

Needed so we can reserve the memory.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Raul E Rangel 2021-02-05 15:53:04 -07:00 committed by Felix Held
parent 899be1b352
commit b9e8044b28
1 changed files with 3 additions and 0 deletions
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3
src/soc/amd/cezanne/romstage.c
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <amdblocks/memmap.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <console/console.h> #include <console/console.h>
#include <console/uart.h> #include <console/uart.h>
@ -33,5 +34,7 @@ asmlinkage void car_stage_entry(void)
fsp_memory_init(acpi_is_wakeup_s3()); fsp_memory_init(acpi_is_wakeup_s3());
memmap_stash_early_dram_usage();
run_ramstage(); run_ramstage();
} }