diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 1eb30a1ff7..e41b801a8b 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -112,18 +112,15 @@ int intel_early_me_uma_size(void)
 
 static inline void set_global_reset(int enable)
 {
-	u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
-
-	/* Clear CF9 Without Resume Well Reset Enable */
-	etr3 &= ~ETR3_CWORWRE;
+	u32 pmir = pci_read_config32(PCH_LPC_DEV, PMIR);
 
 	/* CF9GR indicates a Global Reset */
 	if (enable)
-		etr3 |= ETR3_CF9GR;
+		pmir |= PMIR_CF9GR;
 	else
-		etr3 &= ~ETR3_CF9GR;
+		pmir &= ~PMIR_CF9GR;
 
-	pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+	pci_write_config32(PCH_LPC_DEV, PMIR, pmir);
 }
 
 int intel_early_me_init_done(u8 status)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3738a13dbd..e1d9db4378 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -129,9 +129,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
 #define GEN_PMCON_1		0xa0
 #define GEN_PMCON_2		0xa2
 #define GEN_PMCON_3		0xa4
-#define ETR3			0xac
-#define  ETR3_CWORWRE		(1 << 18)
-#define  ETR3_CF9GR		(1 << 20)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
 
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)