From b9edd8be67c0f6c503451af75e6c1609fc6ec7ad Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Tue, 3 Dec 2019 13:32:11 +0200
Subject: [PATCH] asrock/imb-a180: Switch away from ROMCC_BOOTBLOCK
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Change-Id: I603e6c83d72cf6c1d8f8c6eef652fdf954a3a284
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asrock/imb-a180/Kconfig         |  1 -
 src/mainboard/asrock/imb-a180/Makefile.inc    |  2 ++
 .../imb-a180/{romstage.c => bootblock.c}      | 26 ++++---------------
 3 files changed, 7 insertions(+), 22 deletions(-)
 rename src/mainboard/asrock/imb-a180/{romstage.c => bootblock.c} (69%)

diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig
index b753424c84..8fca61c899 100644
--- a/src/mainboard/asrock/imb-a180/Kconfig
+++ b/src/mainboard/asrock/imb-a180/Kconfig
@@ -17,7 +17,6 @@ if BOARD_ASROCK_IMB_A180
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select ROMCC_BOOTBLOCK
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/mainboard/asrock/imb-a180/Makefile.inc b/src/mainboard/asrock/imb-a180/Makefile.inc
index f8895faa92..4dde2cfd1e 100644
--- a/src/mainboard/asrock/imb-a180/Makefile.inc
+++ b/src/mainboard/asrock/imb-a180/Makefile.inc
@@ -13,6 +13,8 @@
 # GNU General Public License for more details.
 #
 
+bootblock-y += bootblock.c
+
 romstage-y += buildOpts.c
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/bootblock.c
similarity index 69%
rename from src/mainboard/asrock/imb-a180/romstage.c
rename to src/mainboard/asrock/imb-a180/bootblock.c
index 5b9a2263e5..f6bd5c40de 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/bootblock.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -13,35 +11,21 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
+#include <amdblocks/acpimmio.h>
+#include <bootblock_common.h>
+#include <device/pnp_type.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627uhg/w83627uhg.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
 
-void board_BeforeAgesa(struct sysinfo *cb)
+void bootblock_mainboard_early_init(void)
 {
 	volatile u32 *addr32;
 	u32 t32;
 
-	/* Set LPC decode enables. */
-	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-	pci_write_config32(dev, 0x44, 0xff03ffd5);
-
-	/* Enable the AcpiMmio space */
-	outb(0x24, 0xcd6);
-	outb(0x1, 0xcd7);
-
 	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
-	outb(0xea, 0xcd6);
-	outb(0x1, 0xcd7);
+	pm_write8(0xea, 0x1);
 
 	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
 	addr32 = (u32 *)0xfed80e28;