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mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED 

Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, the PSPP policy will be switched to balanced again.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-03-07 17:03:27 +01:00
parent 7c477a9d1a
commit b9ee6f351b
1 changed files with 1 additions and 1 deletions
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src/mainboard/amd/chausie/devicetree.cb
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@ -24,7 +24,7 @@ chip soc/amd/sabrina
register "s0ix_enable" = "true"
register "pspp_policy" = "DXIO_PSPP_BALANCED"
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
device domain 0 on
device ref iommu on end