mb/google/guybrush: Add SoC thermal zone

The time constant values were taken from the zork thermal.asl.

BUG=b:186166365
TEST=Boot guybrush to OS and verify logs look correct
      thermal-0294 thermal_trips_update  : Found critical threshold [3641]
      thermal-0321 thermal_trips_update  : No hot threshold
      thermal-0200 thermal_get_temperatur: Temperature is 3060 dK
      thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS
      thermal-0200 thermal_get_temperatur: Temperature is 3060 dK
    thermal LNXTHERM:00: registered as thermal_zone0
    ACPI: Thermal Zone [TM00] (33 C)
      thermal-0200 thermal_get_temperatur: Temperature is 3070 dK

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Raul E Rangel 2021-05-12 17:07:39 -06:00 committed by Patrick Georgi
parent cecadfd42a
commit ba102237e6
2 changed files with 58 additions and 1 deletions

View File

@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select DISABLE_KEYBOARD_RESET_PIN
select DISABLE_SPI_FLASH_ROM_SHARING
select DRIVERS_ACPI_THERMAL_ZONE
select DRIVERS_AMD_I2S_MACHINE_DEV
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_I2C_GENERIC

View File

@ -152,7 +152,7 @@ chip soc/amd/cezanne
device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on end
device pnp 0c09.0 alias chrome_ec on end
end
end
end # domain
@ -168,4 +168,60 @@ chip soc/amd/cezanne
device ref uart_0 on end # UART0
# See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/guybrush/baseboard.c;l=221
# for the EC configuration.
#
# EC is configured to power off the system at 105C, so add a two degree
# buffer so the OS can gracefully shutdown.
#
# EC is configured to assert PROCHOT at 100C. That drastically lowers
# performance. Instead we will tell the OS to start throttling the CPUs
# at 95C in hopes that we don't hit the PROCHOT limit.
#
# We set use_acpi1_thermal_zone_scope because the Chrome ec.asl
# performs a `Notify` to the `_\TZ` scope.
chip drivers/acpi/thermal_zone
register "description" = ""SOC""
use chrome_ec as temperature_controller
register "sensor_id" = "0"
register "polling_period" = "10"
register "critical_temperature" = "103"
register "passive_config.temperature" = "95"
register "use_acpi1_thermal_zone_scope" = "true"
device generic 0 on end
end
chip drivers/acpi/thermal_zone
register "description" = ""Charger""
use chrome_ec as temperature_controller
register "sensor_id" = "1"
register "polling_period" = "10"
register "critical_temperature" = "103"
register "passive_config.temperature" = "95"
register "use_acpi1_thermal_zone_scope" = "true"
device generic 1 on end
end
chip drivers/acpi/thermal_zone
register "description" = ""Memory""
use chrome_ec as temperature_controller
register "sensor_id" = "2"
register "polling_period" = "10"
register "critical_temperature" = "103"
register "passive_config.temperature" = "95"
register "use_acpi1_thermal_zone_scope" = "true"
device generic 2 on end
end
chip drivers/acpi/thermal_zone
register "description" = ""CPU""
use chrome_ec as temperature_controller
register "sensor_id" = "3"
register "polling_period" = "10"
register "critical_temperature" = "103"
register "passive_config.temperature" = "95"
register "use_acpi1_thermal_zone_scope" = "true"
device generic 3 on end
end
end # chip soc/amd/cezanne