mb/google/dedede/var/driblee: Configure USB port settings
Update the USB port configuration based on driblee schematic. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 1 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: None USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:195622487, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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chip soc/intel/jasperlake
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# USB Port Configuration
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # None
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # None
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # None
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera (UFC)
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # None
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register "usb3_ports[1]" = "USB3_PORT_EMPTY" # None
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # None
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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@ -32,6 +41,29 @@ chip soc/intel/jasperlake
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register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
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device domain 0 on
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device pci 14.0 on
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chip drivers/usb/acpi
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device usb 0.0 on
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chip drivers/usb/acpi
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device usb 2.1 off end
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end
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chip drivers/usb/acpi
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device usb 2.3 off end
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end
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chip drivers/usb/acpi
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register "desc" = ""Camera (UFC)""
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register "type" = "UPC_TYPE_INTERNAL"
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device usb 2.5 on end
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end
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chip drivers/usb/acpi
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device usb 3.1 off end
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end
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chip drivers/usb/acpi
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device usb 3.3 off end
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end
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end
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end
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end # USB xHCI
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device pci 15.0 on end
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device pci 1e.2 off end # GSPI 0
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device pci 1f.0 on
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