diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc
index 9ee6e81a08..22ba2cc436 100644
--- a/src/soc/amd/sabrina/Makefile.inc
+++ b/src/soc/amd/sabrina/Makefile.inc
@@ -12,7 +12,6 @@ all-y		+= aoac.c
 
 bootblock-y	+= bootblock.c
 bootblock-y	+= early_fch.c
-bootblock-y	+= espi_util.c
 bootblock-y	+= gpio.c
 bootblock-y	+= i2c.c
 bootblock-y	+= reset.c
diff --git a/src/soc/amd/sabrina/espi_util.c b/src/soc/amd/sabrina/espi_util.c
deleted file mode 100644
index 41289aeb26..0000000000
--- a/src/soc/amd/sabrina/espi_util.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Check if this is still correct */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/lpc.h>
-#include <device/pci_ops.h>
-#include <soc/espi.h>
-#include <soc/lpc.h>
-#include <soc/pci_devs.h>
-#include <soc/southbridge.h>
-#include <types.h>
-
-void espi_disable_lpc_ldrq(void)
-{
-	/* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped
-	   on Picasso and older compared to Renoir/Cezanne and newer */
-	uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS);
-	dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN);
-	dword |= LPC_LDRQ0_PD_EN;
-	pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);
-}
-
-void espi_switch_to_spi2_pads(void)
-{
-	/* Use SPI2 pins for eSPI */
-	uint32_t dword = pm_read32(PM_SPI_PAD_PU_PD);
-	dword |= PM_ESPI_CS_USE_DATA2;
-	pm_write32(PM_SPI_PAD_PU_PD, dword);
-
-	/* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */
-	dword = pm_read32(PM_ACPI_CONF);
-	dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL;
-	pm_write32(PM_ACPI_CONF, dword);
-}
diff --git a/src/soc/amd/sabrina/include/soc/espi.h b/src/soc/amd/sabrina/include/soc/espi.h
deleted file mode 100644
index 7edef44611..0000000000
--- a/src/soc/amd/sabrina/include/soc/espi.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* TODO: Check if this is still correct */
-
-#ifndef AMD_SABRINA_ESPI_H
-#define AMD_SABRINA_ESPI_H
-
-void espi_disable_lpc_ldrq(void);
-void espi_switch_to_spi2_pads(void);
-
-#endif /* AMD_SABRINA_ESPI_H */
diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h
index 4ce58dd9d1..869af0bc87 100644
--- a/src/soc/amd/sabrina/include/soc/southbridge.h
+++ b/src/soc/amd/sabrina/include/soc/southbridge.h
@@ -75,7 +75,6 @@
 #define   PM_ACPI_USE_GATED_ALINK_CLK	BIT(30)
 #define   PM_ACPI_DELAY_GPP_OFF_TIME	BIT(31)
 #define PM_SPI_PAD_PU_PD		0x90
-#define   PM_ESPI_CS_USE_DATA2		BIT(16)
 #define PM_LPC_GATING			0xec
 #define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
 #define   PM_LPC_A20_EN			BIT(1)