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soc/amd/common/lpc: Add decode disable function 

It is already trivial to set D14F3x44 to 0, but add a function to wipe
both that and the settings in D14F3x48, along with x48's associated
addresses.

Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Marshall Dawson 2019-09-04 11:00:06 -06:00 committed by Martin Roth
parent 5aacda4b98
commit ba2533f0ee
2 changed files with 23 additions and 0 deletions
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4
src/soc/amd/common/block/include/amdblocks/lpc.h
View File

@ -68,6 +68,7 @@
#define DECODE_IO_PORT_ENABLE2 BIT(18) #define DECODE_IO_PORT_ENABLE2 BIT(18)
#define DECODE_IO_PORT_ENABLE1 BIT(17) #define DECODE_IO_PORT_ENABLE1 BIT(17)
#define DECODE_IO_PORT_ENABLE0 BIT(16) #define DECODE_IO_PORT_ENABLE0 BIT(16)
#define LPC_SYNC_TIMEOUT_COUNT_MASK (0xff << 8)
#define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) #define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7)
#define LPC_DECODE_RTC_IO_ENABLE BIT(6) #define LPC_DECODE_RTC_IO_ENABLE BIT(6)
#define DECODE_MEM_PORT_ENABLE0 BIT(5) #define DECODE_MEM_PORT_ENABLE0 BIT(5)
@ -134,6 +135,9 @@
#define PREFETCH_EN_SPI_FROM_HOST BIT(0) #define PREFETCH_EN_SPI_FROM_HOST BIT(0)
#define T_START_ENH BIT(3) #define T_START_ENH BIT(3)
/* Clear all decoding to the LPC bus and erase any range registers associated
* with the enable bits. */
void lpc_disable_decodes(void);
/* LPC is typically enabled very early, but this function is last opportunity */ /* LPC is typically enabled very early, but this function is last opportunity */
void soc_late_lpc_bridge_enable(void); void soc_late_lpc_bridge_enable(void);
void lpc_enable_port80(void); void lpc_enable_port80(void);

19
src/soc/amd/common/block/lpc/lpc_util.c
View File

@ -170,6 +170,25 @@ void lpc_enable_decode(uint32_t decodes)
pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes);
} }
/*
* Clear all decoding to the LPC bus and erase any range registers associated
* with the enable bits.
*/
void lpc_disable_decodes(void)
{
uint32_t reg;
lpc_enable_decode(0);
reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
reg &= LPC_SYNC_TIMEOUT_COUNT_MASK | LPC_SYNC_TIMEOUT_COUNT_ENABLE;
pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg);
/* D14F3x48 enables ranges configured in additional registers */
pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0);
pci_write_config32(_LPCB_DEV, LPC_MEM_PORT0, 0);
pci_write_config32(_LPCB_DEV, LPC_WIDEIO2_GENERIC_PORT, 0);
}
uintptr_t lpc_spibase(void) uintptr_t lpc_spibase(void)
{ {
u32 base, enables; u32 base, enables;