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mb/google/faffy: Enable USB2 port6 

Due to faffy has PL-2303 connect to USB2 port6(count from port0),
needs to enable it.

BUG=b:159760559
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
     boot on puff board

Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Tim Chen 2020-06-24 14:26:03 +08:00 committed by Patrick Georgi
parent 346f391642
commit ba26aa8981
1 changed files with 8 additions and 1 deletions
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9
src/mainboard/google/hatch/variants/faffy/overridetree.cb
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@ -62,7 +62,14 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A port 0
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[6]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # PL2303
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "{