mb/acer/g43t-am3: add Acer G43T-AM3 mainboard
Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800 desktop model of which I only own the mainboard. The silkscreen label calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called Acer EG43M. The Aspire M5800 model seems to use the same mainboard. The BIOS you can download from Acer is identical for both. Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4, Q45T-AM, to name a few. ECS has some models that are obiously based on the same design, e.g. G43T-WM and G43T-M. This model is a microATX-sized board with an LGA 775 socket, four DDR3 DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based on the Intel G43 chipset. The port was started by copying mb/intel/dg43gt (not going to lie here) and adapting things by looking at dumps from the system when running with the vendor BIOS. Serial console output is possible by soldering to a point at the corresponding Super I/O pin. The service manual for the board was helpful for setting the correct PCI IRQ links. It can be found publicly on the internet as the "Acer Aspire M3800 Service Manual". Working: - CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333 - Native raminit - All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB) - PS/2 mouse - PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500) - USB ports (8 internal, 4 external) - All six SATA ports - Intel GbE - Both PCI ports with various cards (Ethernet, audio, USB, VGA) - Integrated graphics (libgfxinit) - HDMI and VGA ports - boot with PCIe graphics and SeaBIOS - boot with PCI VGA and SeaBIOS - Both PCIe ports - Flashing with flashrom - Rear audio output - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Temperature readings (including PECI) - Super I/O EC automatic fan control - S3 suspend/resume - Poweroff Not working: - Resource issues with the VGA BIOS of a PCI rv100-based card - Super I/O voltage reading conversions Untested: - The other audio jacks or the front panel header - On-board Firewire - EHCI debug - VBT (was extracted and added, but don't know how to test) - Super I/O GPIOs Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michael Büchler
Patrick Georgi
parent
d51449d017
commit
ba49d859ee
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## SPDX-License-Identifier: GPL-2.0-only
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if VENDOR_ACER
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choice
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prompt "Mainboard model"
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source "src/mainboard/acer/*/Kconfig.name"
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endchoice
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source "src/mainboard/acer/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "Acer"
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endif # VENDOR_ACER
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@ -0,0 +1,2 @@
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config VENDOR_ACER
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bool "Acer"
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_ACER_G43T_AM3
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801JX
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select SUPERIO_ITE_IT8720F
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select DRIVERS_I2C_CK505
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_USES_IFD_GBE_REGION
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config VGA_BIOS_ID
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string
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default "8086,2e22"
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config MAINBOARD_DIR
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string
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default "acer/g43t-am3"
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config MAINBOARD_PART_NUMBER
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string
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default "G43T-AM3"
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endif # BOARD_ACER_G43T_AM3
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config BOARD_ACER_G43T_AM3
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bool "G43T-AM3"
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# SPDX-License-Identifier: GPL-2.0-only
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ramstage-y += cstates.c
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romstage-y += gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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/* dummy */
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This is board specific information:
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* IRQ routing for the 0:1e.0 PCI bridge of the ICH10
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*/
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If (PICM) {
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Return (Package() {
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/* PCI slot */
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Package() { 0x0001ffff, 0, 0, 0x14},
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Package() { 0x0001ffff, 1, 0, 0x15},
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Package() { 0x0001ffff, 2, 0, 0x16},
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Package() { 0x0001ffff, 3, 0, 0x17},
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Package() { 0x0002ffff, 0, 0, 0x15},
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Package() { 0x0002ffff, 1, 0, 0x16},
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Package() { 0x0002ffff, 2, 0, 0x17},
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Package() { 0x0002ffff, 3, 0, 0x14},
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})
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} Else {
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Return (Package() {
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
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Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
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Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
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Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
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Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
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Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
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Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
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})
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#undef SUPERIO_DEV
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#undef SUPERIO_PNP_BASE
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#undef IT8720F_SHOW_SP1
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#undef IT8720F_SHOW_SP2
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#undef IT8720F_SHOW_EC
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#undef IT8720F_SHOW_KBCK
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#undef IT8720F_SHOW_KBCM
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#undef IT8720F_SHOW_GPIO
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#undef IT8720F_SHOW_CIR
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define IT8720F_SHOW_EC 1
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#define IT8720F_SHOW_KBCK 1
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#define IT8720F_SHOW_KBCM 1
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#define IT8720F_SHOW_GPIO 1
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#include <superio/ite/it8720f/acpi/superio.asl>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <southbridge/intel/i82801jx/nvs.h>
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void acpi_create_gnvs(struct global_nvs *gnvs)
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{
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gnvs->pwrs = 1; /* Power state (AC = 1) */
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gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
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gnvs->apic = 1; /* Enable APIC */
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gnvs->mpen = 1; /* Enable Multi Processing */
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}
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Category: desktop
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Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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nmi=Enable
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sata_mode=AHCI
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gfx_uma_size=64M
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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# coreboot config options: southbridge
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408 1 e 10 sata_mode
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409 2 e 7 power_on_after_fail
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411 1 e 1 nmi
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# coreboot config options: cpu
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# coreboot config options: northbridge
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432 4 e 11 gfx_uma_size
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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10 0 AHCI
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10 1 Compatible
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11 1 4M
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11 2 8M
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11 3 16M
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11 4 32M
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11 5 48M
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11 6 64M
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11 7 128M
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11 8 256M
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11 9 96M
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11 10 160M
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11 11 224M
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11 12 352M
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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int get_cst_entries(acpi_cstate_t **entries)
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{
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return 0;
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}
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Binary file not shown.
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x # CPU
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device lapic 0xacac off end
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end
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end
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device domain 0 on # PCI domain
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subsystemid 0x8086 0x0028 inherit
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device pci 0.0 on end # Host Bridge
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device pci 2.0 on end # Integrated graphics controller
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device pci 2.1 on end # Integrated graphics controller 2
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device pci 3.0 off end # ME
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device pci 3.1 off end # ME
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chip southbridge/intel/i82801jx # Southbridge
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register "gpe0_en" = "0x40"
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# Set AHCI mode.
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register "sata_port_map" = "0x3f"
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register "sata_clock_request" = "0"
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# Enable PCIe ports 0,1 as slots.
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register "pcie_slot_implemented" = "0x3"
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# "Additional LPC IO decode ranges": used for SuperIO's
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# Environment Controller on 0xa15/0xa16
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register "gen1_dec" = "0x00fc0a01"
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device pci 19.0 on end # GBE
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device pci 1a.0 on end # USB
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device pci 1a.1 on end # USB
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device pci 1a.2 on end # USB
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device pci 1a.7 on end # USB
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device pci 1b.0 on end # Audio
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device pci 1c.0 on end # PCIe 1
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device pci 1c.1 on end # PCIe 2
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device pci 1c.2 off end # PCIe 3
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device pci 1c.3 off end # PCIe 4
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device pci 1c.4 off end # PCIe 5
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device pci 1c.5 off end # PCIe 6
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device pci 1d.0 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.2 on end # USB
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device pci 1d.7 on end # USB
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/ite/it8720f # Super I/O
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register "ec.smbus_en" = "1"
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register "ec.smbus_24mhz" = "1"
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register "TMPIN1.mode" = "THERMAL_DIODE"
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register "TMPIN2.mode" = "THERMAL_RESISTOR"
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register "TMPIN3.mode" = "THERMAL_PECI"
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register "TMPIN3.offset" = "100"
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register "TMPIN3.min" = "0"
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register "TMPIN3.max" = "100"
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register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan
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register "FAN1.smart.tmpin" = "3"
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register "FAN1.smart.tmp_off" = "0"
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register "FAN1.smart.tmp_start" = "50"
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register "FAN1.smart.tmp_full" = "90"
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register "FAN1.smart.tmp_delta" = "3"
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register "FAN1.smart.full_lmt" = "1"
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register "FAN1.smart.smoothing" = "0"
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register "FAN1.smart.pwm_start" = "30"
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register "FAN1.smart.slope" = "0x0d"
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register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # System fan
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register "FAN2.smart.tmpin" = "2"
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register "FAN2.smart.tmp_off" = "0"
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register "FAN2.smart.tmp_start" = "40"
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register "FAN2.smart.tmp_full" = "90"
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register "FAN2.smart.tmp_delta" = "2"
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register "FAN2.smart.full_lmt" = "0"
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register "FAN2.smart.smoothing" = "0"
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register "FAN2.smart.pwm_start" = "48"
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register "FAN2.smart.slope" = "0x20"
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register "FAN3.mode" = "FAN_MODE_OFF" # Not connected
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register "ec.vin_mask" = "VIN_ALL"
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 off end # COM 1
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device pnp 2e.2 off end # COM 2
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device pnp 2e.3 off end # Parallel port
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device pnp 2e.4 on # Environment controller
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io 0x60 = 0xa10
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io 0x62 = 0xa00
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irq 0x70 = 0x00
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irq 0xf0 = 0x00
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irq 0xf1 = 0x00
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irq 0xf2 = 0x00
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irq 0xf3 = 0x00
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irq 0xf4 = 0x60
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irq 0xf5 = 0x00
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irq 0xf6 = 0x00
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x060
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irq 0x70 = 0x1
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io 0x62 = 0x064
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irq 0xf0 = 0x00
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 0x0c
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irq 0xf0 = 0x00
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end
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device pnp 2e.7 on # GPIO
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io 0x60 = 0x000
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io 0x62 = 0xa20
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io 0x64 = 0xa30
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irq 0xc0 = 0x01 # Simple IO Set 1
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irq 0xc1 = 0x0c # Simple IO Set 2
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irq 0xc2 = 0x70 # Simple IO Set 3
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irq 0xc3 = 0x00 # Simple IO Set 4
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irq 0xc8 = 0x01 # Simple IO Set 1 Output
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irq 0xc9 = 0x0c # Simple IO Set 2 Output
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irq 0xca = 0x00 # Simple IO Set 3 Output
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irq 0xcb = 0x00 # Simple IO Set 4 Output
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irq 0xf0 = 0x00
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irq 0xf1 = 0x00
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irq 0xf2 = 0x00
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irq 0xf3 = 0x00
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irq 0xf4 = 0x00
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irq 0xf5 = 0x00
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irq 0xf6 = 0x00
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irq 0xf7 = 0x00
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irq 0xf8 = 0x12
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irq 0xf9 = 0x02
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irq 0xfa = 0x13
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irq 0xfb = 0x02
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#irq 0xfc = 0xef # VID Input
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irq 0xfd = 0x00
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irq 0xfe = 0x00
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end
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device pnp 2e.a off end # CIR
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end
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end
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device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5)
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device pci 1f.3 on # SMBus
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chip drivers/i2c/ck505 # IDT CV194
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register "mask" = "{ 0xff, 0xff, 0xff, 0x00,
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0xff, 0x00, 0x00, 0x00,
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0x00, 0xff, 0xff, 0xff,
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0x00, 0xff }"
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register "regs" = "{ 0x57, 0xd9, 0xfe, 0xff,
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0xff, 0x00, 0x00, 0x00,
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0x00, 0x24, 0x7d, 0x96,
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0x00, 0x9d }"
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device i2c 69 on end
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end
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end
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device pci 1f.4 off end
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device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode)
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device pci 1f.6 off end # Thermal Subsystem
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end
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end
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end
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20090811 // OEM revision
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)
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{
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// global NVS and variables
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#include <southbridge/intel/common/acpi/platform.asl>
|
||||
#include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <northbridge/intel/x4x/acpi/x4x.asl>
|
||||
#include <southbridge/intel/i82801jx/acpi/ich10.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include <superio/ite/it8720f/it8720f.h>
|
||||
|
||||
#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
/* Set up GPIOs on Super I/O. */
|
||||
ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO set 1
|
||||
ite_reg_write(GPIO_DEV, 0x26, 0x0c); // GPIO set 2
|
||||
ite_reg_write(GPIO_DEV, 0x27, 0x70); // GPIO set 3
|
||||
ite_reg_write(GPIO_DEV, 0x28, 0x40); // GPIO set 4
|
||||
ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO set 5
|
||||
|
||||
/* Enable 3VSB during Suspend-to-RAM */
|
||||
ite_enable_3vsbsw(GPIO_DEV);
|
||||
|
||||
/* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */
|
||||
ite_delay_pwrgd3(GPIO_DEV);
|
||||
}
|
||||
|
||||
void mb_get_spd_map(u8 spd_map[4])
|
||||
{
|
||||
spd_map[0] = 0x50;
|
||||
spd_map[1] = 0x51;
|
||||
spd_map[2] = 0x52;
|
||||
spd_map[3] = 0x53;
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_GPIO,
|
||||
.gpio20 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio9 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio18 = GPIO_DIR_OUTPUT,
|
||||
.gpio20 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio9 = GPIO_LEVEL_HIGH,
|
||||
.gpio18 = GPIO_LEVEL_HIGH,
|
||||
.gpio20 = GPIO_LEVEL_LOW,
|
||||
.gpio27 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio6 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
.gpio18 = GPIO_BLINK,
|
||||
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_NATIVE,
|
||||
.gpio36 = GPIO_MODE_NATIVE,
|
||||
.gpio37 = GPIO_MODE_NATIVE,
|
||||
.gpio38 = GPIO_MODE_NATIVE,
|
||||
.gpio39 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_NATIVE,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio56 = GPIO_MODE_GPIO,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_INPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_OUTPUT,
|
||||
.gpio56 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
.gpio60 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio49 = GPIO_LEVEL_HIGH,
|
||||
.gpio60 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
},
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0888,
|
||||
0x1025024c, // Subsystem ID
|
||||
14, // Number of entries
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x11, 0x014b7140),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x01011012),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x01016011),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x01012014),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19851),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x0181305f),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x18567130),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
|
||||
/* HDMI */
|
||||
0x80862803,
|
||||
0x80860101,
|
||||
1,
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x03, 0x18560010)
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
|
||||
const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
|
||||
Loading…
Reference in New Issue