AGESA f14 vendorcode: Only have f14 Ontario config
Change-Id: I8cf2f23d785e934371dfa687483491cd22b9863d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
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@ -54,39 +54,10 @@
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* Check to validate the definition
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*/
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#define OPTION_C6_STATE_FEAT
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#define F12_C6_STATE_SUPPORT
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#define F14_C6_STATE_SUPPORT
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#define F15_C6_STATE_SUPPORT
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#if OPTION_C6_STATE == TRUE
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#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
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#ifdef OPTION_FAMILY12H
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#if OPTION_FAMILY12H == TRUE
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#if OPTION_FAMILY12H_LN == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
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#undef OPTION_C6_STATE_FEAT
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#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
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extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
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#undef F12_C6_STATE_SUPPORT
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#define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
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#if OPTION_EARLY_SAMPLES == TRUE
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extern F_F12_ES_C6_INIT F12C6A0Workaround;
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CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
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{
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F12C6A0Workaround
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};
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#else
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CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
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{
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(PF_F12_ES_C6_INIT) CommonVoid
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};
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#endif
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#endif
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#endif
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#endif
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#ifdef OPTION_FAMILY14H
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#if OPTION_FAMILY14H == TRUE
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@ -119,26 +90,12 @@
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#endif
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#endif
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#ifdef OPTION_FAMILY15H
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#if OPTION_FAMILY15H == TRUE
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#if OPTION_FAMILY15H_OR == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
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#undef OPTION_C6_STATE_FEAT
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#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
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extern CONST C6_FAMILY_SERVICES ROMDATA F15C6Support;
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#undef F15_C6_STATE_SUPPORT
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#define F15_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15C6Support},
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#endif
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#endif
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#endif
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#endif
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#endif
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CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
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{
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F12_C6_STATE_SUPPORT
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F14_C6_STATE_SUPPORT
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F15_C6_STATE_SUPPORT
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{0, NULL}
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};
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@ -54,40 +54,10 @@
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* Check to validate the definition
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*/
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#define OPTION_CPB_FEAT
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#define F10_CPB_SUPPORT
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#define F12_CPB_SUPPORT
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#define F14_ON_CPB_SUPPORT
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#define F15_CPB_SUPPORT
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#if OPTION_CPB == TRUE
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#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
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// Family 10h
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#ifdef OPTION_FAMILY10H
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#if OPTION_FAMILY10H == TRUE
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#if OPTION_FAMILY10H_PH == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
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#undef OPTION_CPB_FEAT
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#define OPTION_CPB_FEAT &CpuFeatureCpb,
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extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
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#undef F10_CPB_SUPPORT
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#define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
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#endif
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#endif
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#endif
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// Family 12h
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#ifdef OPTION_FAMILY12H
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#if OPTION_FAMILY12H == TRUE
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#if OPTION_FAMILY12H_LN == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
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#undef OPTION_CPB_FEAT
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#define OPTION_CPB_FEAT &CpuFeatureCpb,
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extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
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#undef F12_CPB_SUPPORT
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#define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
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#endif
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#endif
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#endif
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// Family 14h
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#ifdef OPTION_FAMILY14H
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@ -103,29 +73,12 @@
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#endif
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#endif
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// Family 15h
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#ifdef OPTION_FAMILY15H
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#if OPTION_FAMILY15H == TRUE
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#if OPTION_FAMILY15H_OR == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
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#undef OPTION_CPB_FEAT
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#define OPTION_CPB_FEAT &CpuFeatureCpb,
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extern CONST CPB_FAMILY_SERVICES ROMDATA F15CpbSupport;
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#undef F15_CPB_SUPPORT
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#define F15_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15CpbSupport},
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#endif
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#endif
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#endif
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#endif
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#endif
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CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
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{
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F10_CPB_SUPPORT
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F12_CPB_SUPPORT
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F14_ON_CPB_SUPPORT
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F15_CPB_SUPPORT
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{0, NULL}
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};
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@ -54,63 +54,13 @@
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* Check to validate the definition
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*/
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#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
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#define F10_BL_CPU_CFOH_SUPPORT
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#define F10_DA_CPU_CFOH_SUPPORT
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#define F10_CPU_CFOH_SUPPORT
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#define F15_OR_CPU_CFOH_SUPPORT
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#if OPTION_CPU_CFOH == TRUE
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#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
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#ifdef OPTION_FAMILY10H
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#if OPTION_FAMILY10H == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
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#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
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#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
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#if OPTION_FAMILY10H_BL == TRUE
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extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
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#undef F10_BL_CPU_CFOH_SUPPORT
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#define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
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#endif
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#if OPTION_FAMILY10H_DA == TRUE
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extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
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#undef F10_DA_CPU_CFOH_SUPPORT
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#define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
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#endif
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#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
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extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
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#undef F10_CPU_CFOH_SUPPORT
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#define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
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#endif
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#endif
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#endif
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#ifdef OPTION_FAMILY15H
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#if OPTION_FAMILY15H == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
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#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
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#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
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#if OPTION_FAMILY15H_OR == TRUE
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extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15CacheFlushOnHalt;
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#undef F15_OR_CPU_CFOH_SUPPORT
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#define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15CacheFlushOnHalt},
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#endif
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#endif
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#endif
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#endif
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#endif
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CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
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{
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F10_BL_CPU_CFOH_SUPPORT
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F10_DA_CPU_CFOH_SUPPORT
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F10_CPU_CFOH_SUPPORT
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F15_OR_CPU_CFOH_SUPPORT
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{0, NULL}
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};
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CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
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{
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(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
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* Check to validate the definition
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*/
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#define OPTION_CPU_CORE_LEVELING_FEAT
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#define F10_REVE_CPU_CORELEVELING_SUPPORT
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#define F10_REVD_CPU_CORELEVELING_SUPPORT
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#define F10_REVC_CPU_CORELEVELING_SUPPORT
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#define F15_CPU_CORELEVELING_SUPPORT
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#if OPTION_CPU_CORELEVLING == TRUE
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#if (AGESA_ENTRY_INIT_EARLY == TRUE)
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// Family 10h
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#if OPTION_FAMILY10H == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
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#undef OPTION_CPU_CORE_LEVELING_FEAT
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#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
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#if OPTION_FAMILY10H == TRUE
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#if OPTION_FAMILY10H_HY == TRUE
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extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
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#undef F10_REVD_CPU_CORELEVELING_SUPPORT
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#define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
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#endif
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#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
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extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
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#undef F10_REVC_CPU_CORELEVELING_SUPPORT
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#define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
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#endif
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#if (OPTION_FAMILY10H_PH == TRUE)
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extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
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#undef F10_REVE_CPU_CORELEVELING_SUPPORT
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#define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
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#endif
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#endif
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#endif
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// Family 15h
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#if OPTION_FAMILY15H == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
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#undef OPTION_CPU_CORE_LEVELING_FEAT
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#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
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extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15CoreLeveling;
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#undef F15_CPU_CORELEVELING_SUPPORT
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#define F15_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15, &F15CoreLeveling},
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#endif
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#endif
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#endif
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CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
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{
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F10_REVE_CPU_CORELEVELING_SUPPORT
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F10_REVD_CPU_CORELEVELING_SUPPORT
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F10_REVC_CPU_CORELEVELING_SUPPORT
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F15_CPU_CORELEVELING_SUPPORT
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{0, NULL}
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};
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CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
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#define CPU_DMI_AP_GET_TYPE4_TYPE7
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#endif
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// Family 10
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#ifdef OPTION_FAMILY10H
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#if OPTION_FAMILY10H == TRUE
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extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
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#define FAM10_DMI_SUPPORT FAM10_ENABLED,
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#define FAM10_DMI_TABLE &ProcFamily10DmiTable,
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#else
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#define FAM10_DMI_SUPPORT
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#define FAM10_DMI_TABLE
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#endif
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#else
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#define FAM10_DMI_SUPPORT
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#define FAM10_DMI_TABLE
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#endif
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// Family 12
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#ifdef OPTION_FAMILY12H
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#if OPTION_FAMILY12H == TRUE
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extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
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#define FAM12_DMI_SUPPORT FAM12_ENABLED,
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#define FAM12_DMI_TABLE &ProcFamily12DmiTable,
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#else
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#define FAM12_DMI_SUPPORT
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#define FAM12_DMI_TABLE
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#endif
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#else
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#define FAM12_DMI_SUPPORT
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#define FAM12_DMI_TABLE
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#endif
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// Family 14
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#ifdef OPTION_FAMILY14H
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#if OPTION_FAMILY14H == TRUE
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#define FAM14_DMI_TABLE
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#endif
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// Family 15
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#ifdef OPTION_FAMILY15H
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#if OPTION_FAMILY15H == TRUE
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extern PROC_FAMILY_TABLE ProcFamily15DmiTable;
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#define FAM15_DMI_SUPPORT FAM15_ENABLED,
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#define FAM15_DMI_TABLE &ProcFamily15DmiTable,
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#else
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#define FAM15_DMI_SUPPORT
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#define FAM15_DMI_TABLE
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#endif
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#else
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#define FAM15_DMI_SUPPORT
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#define FAM15_DMI_TABLE
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#endif
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#else
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OPTION_DMI_FEATURE GetDmiInfoStub;
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OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
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#define USER_DMI_OPTION GetDmiInfoStub
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#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
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#define FAM10_DMI_SUPPORT
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#define FAM10_DMI_TABLE
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#define FAM12_DMI_SUPPORT
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#define FAM12_DMI_TABLE
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#define FAM14_DMI_SUPPORT
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#define FAM14_DMI_TABLE
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#define FAM15_DMI_SUPPORT
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#define FAM15_DMI_TABLE
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#define CPU_DMI_AP_GET_TYPE4_TYPE7
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#endif
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#else
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OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
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#define USER_DMI_OPTION GetDmiInfoStub
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#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
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#define FAM10_DMI_SUPPORT
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#define FAM10_DMI_TABLE
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#define FAM12_DMI_SUPPORT
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#define FAM12_DMI_TABLE
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#define FAM14_DMI_SUPPORT
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#define FAM14_DMI_TABLE
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#define FAM15_DMI_SUPPORT
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#define FAM15_DMI_TABLE
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#define CPU_DMI_AP_GET_TYPE4_TYPE7
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#endif
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/// DMI supported families enum
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typedef enum {
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FAM10_DMI_SUPPORT ///< Conditionally define F10 support
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FAM12_DMI_SUPPORT ///< Conditionally define F12 support
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FAM14_DMI_SUPPORT ///< Conditionally define F14 support
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FAM15_DMI_SUPPORT ///< Conditionally define F15 support
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NUM_DMI_FAMILIES ///< Number of installed families
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} AGESA_DMI_SUPPORTED_FAM;
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/* Declare the Family List. An array of pointers to tables that each describe a family */
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CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
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FAM10_DMI_TABLE
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FAM12_DMI_TABLE
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FAM14_DMI_TABLE
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FAM15_DMI_TABLE
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NULL
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};
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* Check to validate the definition
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*/
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#define GNB_TYPE_LN OPTION_FAMILY12H
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#define GNB_TYPE_LN FALSE
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#define GNB_TYPE_ON OPTION_FAMILY14H
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#define GNB_TYPE_KR FALSE
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#define GNB_TYPE_TN FALSE
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* Check to validate the definition
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*/
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#define OPTION_HT_ASSIST_FEAT
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#define F10_HT_ASSIST_SUPPORT
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#define F15_HT_ASSIST_SUPPORT
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#define HT_ASSIST_AP_DISABLE_CACHE
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#define HT_ASSIST_AP_ENABLE_CACHE
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#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
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#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
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#ifdef OPTION_FAMILY10H
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#if OPTION_FAMILY10H == TRUE
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#if OPTION_FAMILY10H_HY == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
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#undef OPTION_HT_ASSIST_FEAT
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#define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
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extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist;
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#undef F10_HT_ASSIST_SUPPORT
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#define F10_HT_ASSIST_SUPPORT {AMD_FAMILY_10_HY, &F10HtAssist},
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#endif
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#endif
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#endif
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#ifdef OPTION_FAMILY15H
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#if OPTION_FAMILY15H == TRUE
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extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
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#undef OPTION_HT_ASSIST_FEAT
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#define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
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extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F15HtAssist;
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#undef F15_HT_ASSIST_SUPPORT
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#define F15_HT_ASSIST_SUPPORT {AMD_FAMILY_15, &F15HtAssist},
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#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
|
||||
{
|
||||
F10_HT_ASSIST_SUPPORT
|
||||
F15_HT_ASSIST_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
|
||||
|
|
|
@ -79,73 +79,25 @@
|
|||
|
||||
/*
|
||||
* Based on user level options, set Ht internal options.
|
||||
* For now, Family 10h support will assume single module. For multi module,
|
||||
* this will have to be changed to not set non-coherent only.
|
||||
*/
|
||||
#define OPTION_HT_NON_COHERENT_ONLY FALSE
|
||||
|
||||
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
|
||||
/* Fusion Families do not need a non-coherent only option. */
|
||||
#else
|
||||
// Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable.
|
||||
#if OPTION_G34_SOCKET_SUPPORT == FALSE
|
||||
// Hydra has coherent support, other Family 10h should follow MultiSocket support.
|
||||
#if OPTION_MULTISOCKET == FALSE
|
||||
#undef OPTION_HT_NON_COHERENT_ONLY
|
||||
#define OPTION_HT_NON_COHERENT_ONLY TRUE
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macros will generate the correct item reference based on options
|
||||
*/
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
// Select the interface and features
|
||||
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
|
||||
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
|
||||
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
|
||||
#else
|
||||
// Family 10h and 15h
|
||||
#if OPTION_HT_NON_COHERENT_ONLY == FALSE
|
||||
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
|
||||
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
|
||||
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
|
||||
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
|
||||
#endif
|
||||
#endif
|
||||
// Select Northbridge components
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault,
|
||||
#endif
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM10_NB
|
||||
#endif
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM12_NB
|
||||
#endif
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM14_NB
|
||||
#endif
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
|
||||
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
|
||||
#endif
|
||||
#else
|
||||
#define INTERNAL_HT_OPTION_FAM15_NB
|
||||
#endif
|
||||
|
||||
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
|
||||
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
|
||||
|
@ -158,9 +110,6 @@
|
|||
*/
|
||||
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
|
||||
INTERNAL_ONLY_NB_LIST_ITEM \
|
||||
INTERNAL_HT_OPTION_FAM10_NB \
|
||||
INTERNAL_HT_OPTION_FAM15_NB \
|
||||
INTERNAL_HT_OPTION_FAM12_NB \
|
||||
INTERNAL_HT_OPTION_FAM14_NB
|
||||
|
||||
#else
|
||||
|
@ -271,18 +220,13 @@
|
|||
|
||||
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
|
||||
|
||||
#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
#undef OPTION_HT_INIIT_RESET_ENTRY
|
||||
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
|
||||
#define OPTION_HT_INIIT_RESET_ENTRY NULL
|
||||
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
|
||||
#endif
|
||||
|
||||
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
|
||||
#undef OPTION_HT_INIIT_RESET_ENTRY
|
||||
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef AGESA_ENTRY_INIT_RESET
|
||||
|
|
|
@ -54,23 +54,9 @@
|
|||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_HW_C1E_FEAT
|
||||
#define F10_HW_C1E_SUPPORT
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
|
||||
#undef OPTION_HW_C1E_FEAT
|
||||
#define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
|
||||
extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
|
||||
#undef F10_HW_C1E_SUPPORT
|
||||
#define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
|
||||
{
|
||||
F10_HW_C1E_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
|
||||
|
|
|
@ -57,10 +57,6 @@
|
|||
#if (IDSOPT_IDS_ENABLED == TRUE)
|
||||
#if (IDSOPT_CONTROL_ENABLED == TRUE)
|
||||
// Check for all families which include HT Features.
|
||||
#if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
|
||||
#undef M_HTIDS_PORT_OVERRIDE_HOOK
|
||||
#define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
|
||||
#endif
|
||||
#endif
|
||||
#endif // OPTION_IDS_LEVEL
|
||||
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
|
||||
|
@ -98,90 +94,9 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE
|
|||
#define OPTION_IDS_EXTEND_FEATS
|
||||
#endif
|
||||
|
||||
#define OPTION_IDS_FEAT_ECCCTRL\
|
||||
OPTION_IDS_FEAT_ECCCTRL_F10 \
|
||||
OPTION_IDS_FEAT_ECCCTRL_F12 \
|
||||
OPTION_IDS_FEAT_ECCCTRL_F15
|
||||
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
|
||||
OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
|
||||
OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
|
||||
|
||||
#define OPTION_IDS_FEAT_CPB_CTRL\
|
||||
OPTION_IDS_FEAT_CPB_CTRL_F12
|
||||
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL\
|
||||
OPTION_IDS_FEAT_HTC_CTRL_F15
|
||||
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING\
|
||||
OPTION_IDS_FEAT_MEMORY_MAPPING_F15
|
||||
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST\
|
||||
OPTION_IDS_FEAT_HT_ASSIST_F10HY \
|
||||
OPTION_IDS_FEAT_HT_ASSIST_F15
|
||||
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
|
||||
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
|
||||
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 10 feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F10
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
//Ecc symbol size
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
|
||||
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
|
||||
|
||||
//ECC scrub control
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
|
||||
#undef OPTION_IDS_FEAT_ECCCTRL_F10
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//Misc Features
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY
|
||||
#ifdef OPTION_FAMILY10H_HY
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
#undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
|
||||
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
|
||||
&IdsFeatHtAssistBlockPlatformCfgF10Hy,
|
||||
#endif
|
||||
#endif
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 12 feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F12
|
||||
#define OPTION_IDS_FEAT_CPB_CTRL_F12
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
|
||||
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
|
||||
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
|
||||
|
||||
//ECC scrub control
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
|
||||
#undef OPTION_IDS_FEAT_ECCCTRL_F12
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
|
||||
|
||||
#undef OPTION_IDS_FEAT_CPB_CTRL_F12
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
|
||||
#define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 14 feat blocks
|
||||
*
|
||||
|
@ -196,50 +111,6 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE
|
|||
#endif
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Family 15 feat blocks
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL_F15
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F15
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F15
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15;
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15;
|
||||
#undef OPTION_IDS_FEAT_HTC_CTRL_F15
|
||||
#define OPTION_IDS_FEAT_HTC_CTRL_F15\
|
||||
&IdsFeatHtcControlBlockF15,\
|
||||
&IdsFeatHtcControlLateBlockF15,
|
||||
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15;
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15;
|
||||
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15
|
||||
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15\
|
||||
&IdsFeatMemoryMappingPostBeforeBlockF15,\
|
||||
&IdsFeatMemoryMappingChIntlvBlockF15,
|
||||
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15;
|
||||
#undef OPTION_IDS_FEAT_HT_ASSIST_F15
|
||||
#define OPTION_IDS_FEAT_HT_ASSIST_F15\
|
||||
&IdsFeatHtAssistBlockPlatformCfgF15,
|
||||
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15;
|
||||
#undef OPTION_IDS_FEAT_ECCCTRL_F15
|
||||
#define OPTION_IDS_FEAT_ECCCTRL_F15 &IdsFeatEccCtrlBlockF15,
|
||||
|
||||
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15;
|
||||
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
|
||||
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 &IdsFeatEccSymbolSizeBlockF15,
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
|
||||
{
|
||||
IDS_FEAT_UCODE_UPDATE,
|
||||
|
|
|
@ -55,38 +55,10 @@
|
|||
*/
|
||||
|
||||
#define OPTION_IO_CSTATE_FEAT
|
||||
#define F10_IO_CSTATE_SUPPORT
|
||||
#define F12_IO_CSTATE_SUPPORT
|
||||
#define F14_IO_CSTATE_SUPPORT
|
||||
#define F15_IO_CSTATE_SUPPORT
|
||||
|
||||
#if OPTION_IO_CSTATE == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_PH == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
|
||||
#undef F10_IO_CSTATE_SUPPORT
|
||||
#define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
#if OPTION_FAMILY12H_LN == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
|
||||
#undef F12_IO_CSTATE_SUPPORT
|
||||
#define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
|
@ -101,28 +73,12 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
|
||||
#undef OPTION_IO_CSTATE_FEAT
|
||||
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
|
||||
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15IoCstateSupport;
|
||||
#undef F15_IO_CSTATE_SUPPORT
|
||||
#define F15_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15IoCstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
|
||||
{
|
||||
F10_IO_CSTATE_SUPPORT
|
||||
F12_IO_CSTATE_SUPPORT
|
||||
F14_IO_CSTATE_SUPPORT
|
||||
F15_IO_CSTATE_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
|
|
|
@ -54,29 +54,14 @@
|
|||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
|
||||
#define F15_LOW_PWR_PSTATE_SUPPORT
|
||||
|
||||
#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
|
||||
// Family 15h
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if OPTION_FAMILY15H_OR == TRUE
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
|
||||
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
|
||||
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
|
||||
extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15LowPwrPstateSupport;
|
||||
#undef F15_LOW_PWR_PSTATE_SUPPORT
|
||||
#define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15LowPwrPstateSupport},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
|
||||
{
|
||||
F15_LOW_PWR_PSTATE_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -54,59 +54,11 @@
|
|||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_MSG_BASED_C1E_FEAT
|
||||
#define F10_MSG_BASED_C1E_SUPPORT
|
||||
#define F15_MSG_BASED_C1E_SUPPORT
|
||||
#if OPTION_MSG_BASED_C1E == TRUE
|
||||
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
|
||||
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
|
||||
#undef OPTION_MSG_BASED_C1E_FEAT
|
||||
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
|
||||
#undef OPTION_MSG_BASED_C1E_FEAT
|
||||
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if OPTION_FAMILY10H_HY == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
|
||||
#undef F10_MSG_BASED_C1E_SUPPORT
|
||||
#define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
|
||||
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15MsgBasedC1e;
|
||||
#undef F15_MSG_BASED_C1E_SUPPORT
|
||||
#define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15MsgBasedC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
|
||||
{
|
||||
F10_MSG_BASED_C1E_SUPPORT
|
||||
F15_MSG_BASED_C1E_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
|
||||
|
|
|
@ -54,47 +54,11 @@
|
|||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_PRESERVE_MAILBOX_FEAT
|
||||
#define F10_PRESERVE_MAILBOX_SUPPORT
|
||||
#define F15_PRESERVE_MAILBOX_SUPPORT
|
||||
|
||||
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
|
||||
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
|
||||
#undef OPTION_PRESERVE_MAILBOX_FEAT
|
||||
#define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
|
||||
#endif
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
CONST PCI_ADDR ROMDATA F10PreserveMailboxRegisters [] = {
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x168),
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x170),
|
||||
ILLEGAL_SBDFO
|
||||
};
|
||||
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
|
||||
0,
|
||||
TRUE,
|
||||
(PCI_ADDR *)&F10PreserveMailboxRegisters
|
||||
};
|
||||
#undef F10_PRESERVE_MAILBOX_SUPPORT
|
||||
#define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
|
||||
#endif
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
CONST PCI_ADDR ROMDATA F15PreserveMailboxRegisters [] = {
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x168),
|
||||
MAKE_SBDFO (0, 0, 0, 3, 0x170),
|
||||
ILLEGAL_SBDFO
|
||||
};
|
||||
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
|
||||
0,
|
||||
TRUE,
|
||||
(PCI_ADDR *)&F15PreserveMailboxRegisters
|
||||
};
|
||||
#undef F15_PRESERVE_MAILBOX_SUPPORT
|
||||
#define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
|
||||
#endif
|
||||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
|
||||
{
|
||||
F10_PRESERVE_MAILBOX_SUPPORT
|
||||
F15_PRESERVE_MAILBOX_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
|
||||
|
|
|
@ -54,30 +54,12 @@
|
|||
* Check to validate the definition
|
||||
*/
|
||||
|
||||
#define F10_PSTATE_SERVICE_SUPPORT
|
||||
#define F12_PSTATE_SERVICE_SUPPORT
|
||||
#define F14_PSTATE_SERVICE_SUPPORT
|
||||
#define F15_PSTATE_SERVICE_SUPPORT
|
||||
|
||||
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
|
||||
//
|
||||
//Define Pstate CPU Family service
|
||||
//
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
|
||||
#undef F10_PSTATE_SERVICE_SUPPORT
|
||||
#define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY12H
|
||||
#if OPTION_FAMILY12H == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
|
||||
#undef F12_PSTATE_SERVICE_SUPPORT
|
||||
#define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY14H
|
||||
#if OPTION_FAMILY14H == TRUE
|
||||
|
@ -87,13 +69,6 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef OPTION_FAMILY15H
|
||||
#if OPTION_FAMILY15H == TRUE
|
||||
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15PstateServices;
|
||||
#undef F15_PSTATE_SERVICE_SUPPORT
|
||||
#define F15_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15, &F15PstateServices},
|
||||
#endif
|
||||
#endif
|
||||
//
|
||||
//Define ACPI Pstate objects.
|
||||
//
|
||||
|
@ -229,10 +204,7 @@ OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
|
|||
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
|
||||
{
|
||||
F10_PSTATE_SERVICE_SUPPORT
|
||||
F12_PSTATE_SERVICE_SUPPORT
|
||||
F14_PSTATE_SERVICE_SUPPORT
|
||||
F15_PSTATE_SERVICE_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
|
||||
|
|
|
@ -51,23 +51,9 @@
|
|||
* Check to validate the definition
|
||||
*/
|
||||
#define OPTION_SW_C1E_FEAT
|
||||
#define F10_SW_C1E_SUPPORT
|
||||
#if AGESA_ENTRY_INIT_EARLY == TRUE
|
||||
#ifdef OPTION_FAMILY10H
|
||||
#if OPTION_FAMILY10H == TRUE
|
||||
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
|
||||
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
|
||||
#undef OPTION_SW_C1E_FEAT
|
||||
#define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
|
||||
extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
|
||||
#undef F10_SW_C1E_SUPPORT
|
||||
#define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
|
||||
{
|
||||
F10_SW_C1E_SUPPORT
|
||||
{0, NULL}
|
||||
};
|
||||
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
|
||||
|
|
|
@ -72,81 +72,12 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
*/
|
||||
|
||||
/* Default sockets to off */
|
||||
#define OPTION_G34_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_C32_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_S1G3_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_S1G4_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_ASB2_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_FS1_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_FM1_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_FP1_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_FT1_SOCKET_SUPPORT FALSE
|
||||
#define OPTION_AM3_SOCKET_SUPPORT FALSE
|
||||
|
||||
/* Default families to off */
|
||||
#define OPTION_FAMILY10H FALSE
|
||||
#define OPTION_FAMILY12H FALSE
|
||||
#define OPTION_FAMILY14H FALSE
|
||||
#define OPTION_FAMILY15H FALSE
|
||||
|
||||
|
||||
/* Enable the appropriate socket support */
|
||||
#ifdef INSTALL_G34_SOCKET_SUPPORT
|
||||
#if INSTALL_G34_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_G34_SOCKET_SUPPORT
|
||||
#define OPTION_G34_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_C32_SOCKET_SUPPORT
|
||||
#if INSTALL_C32_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_C32_SOCKET_SUPPORT
|
||||
#define OPTION_C32_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_S1G3_SOCKET_SUPPORT
|
||||
#if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_S1G3_SOCKET_SUPPORT
|
||||
#define OPTION_S1G3_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_S1G4_SOCKET_SUPPORT
|
||||
#if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_S1G4_SOCKET_SUPPORT
|
||||
#define OPTION_S1G4_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_ASB2_SOCKET_SUPPORT
|
||||
#if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_ASB2_SOCKET_SUPPORT
|
||||
#define OPTION_ASB2_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_FS1_SOCKET_SUPPORT
|
||||
#if INSTALL_FS1_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_FS1_SOCKET_SUPPORT
|
||||
#define OPTION_FS1_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_FM1_SOCKET_SUPPORT
|
||||
#if INSTALL_FM1_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_FM1_SOCKET_SUPPORT
|
||||
#define OPTION_FM1_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_FP1_SOCKET_SUPPORT
|
||||
#if INSTALL_FP1_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_FP1_SOCKET_SUPPORT
|
||||
#define OPTION_FP1_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_FT1_SOCKET_SUPPORT
|
||||
#if INSTALL_FT1_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_FT1_SOCKET_SUPPORT
|
||||
|
@ -154,31 +85,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef INSTALL_AM3_SOCKET_SUPPORT
|
||||
#if INSTALL_AM3_SOCKET_SUPPORT == TRUE
|
||||
#undef OPTION_AM3_SOCKET_SUPPORT
|
||||
#define OPTION_AM3_SOCKET_SUPPORT TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Enable the appropriate family support */
|
||||
// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
|
||||
#ifdef INSTALL_FAMILY_10_SUPPORT
|
||||
#if INSTALL_FAMILY_10_SUPPORT == TRUE
|
||||
#undef OPTION_FAMILY10H
|
||||
#define OPTION_FAMILY10H TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// F12 is supported in FP1, FS1, & FM1
|
||||
#ifdef INSTALL_FAMILY_12_SUPPORT
|
||||
#if INSTALL_FAMILY_12_SUPPORT == TRUE
|
||||
#undef OPTION_FAMILY12H
|
||||
#define OPTION_FAMILY12H TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// F14 is supported in FT1
|
||||
#ifdef INSTALL_FAMILY_14_SUPPORT
|
||||
#if INSTALL_FAMILY_14_SUPPORT == TRUE
|
||||
|
@ -187,30 +93,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
#endif
|
||||
#endif
|
||||
|
||||
// F15 is supported in G34, C32, & AM3
|
||||
#ifdef INSTALL_FAMILY_15_SUPPORT
|
||||
#if INSTALL_FAMILY_15_SUPPORT == TRUE
|
||||
#undef OPTION_FAMILY15H
|
||||
#define OPTION_FAMILY15H TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Turn off families not required by socket designations */
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
|
||||
#undef OPTION_FAMILY10H
|
||||
#define OPTION_FAMILY10H FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY12H == TRUE)
|
||||
#if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
|
||||
#undef OPTION_FAMILY12H
|
||||
#define OPTION_FAMILY12H FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY14H == TRUE)
|
||||
#if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
|
||||
#undef OPTION_FAMILY14H
|
||||
|
@ -218,62 +100,8 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY15H == TRUE)
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
|
||||
#undef OPTION_FAMILY15H
|
||||
#define OPTION_FAMILY15H FALSE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Check for invalid combinations of socket/family */
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
|
||||
#error No G34 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
|
||||
#error No C32 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == FALSE)
|
||||
#error No S1G3 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == FALSE)
|
||||
#error No S1G4 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == FALSE)
|
||||
#error No ASB2 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY12H == FALSE)
|
||||
#error No FS1 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY12H == FALSE)
|
||||
#error No FM1 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY12H == FALSE)
|
||||
#error No FP1 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY14H == FALSE)
|
||||
|
@ -281,13 +109,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
|
||||
#error No AM3 supported families included in the build
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Process AGESA private data
|
||||
*
|
||||
* Turn on appropriate CPU models and memory controllers,
|
||||
|
@ -295,26 +116,10 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
*/
|
||||
|
||||
/* Default all models to off */
|
||||
#define OPTION_FAMILY10H_BL FALSE
|
||||
#define OPTION_FAMILY10H_DA FALSE
|
||||
#define OPTION_FAMILY10H_HY FALSE
|
||||
#define OPTION_FAMILY10H_PH FALSE
|
||||
#define OPTION_FAMILY10H_RB FALSE
|
||||
#define OPTION_FAMILY12H_LN FALSE
|
||||
#define OPTION_FAMILY14H_ON FALSE
|
||||
#define OPTION_FAMILY15H_OR FALSE
|
||||
|
||||
/* Default all memory controllers to off */
|
||||
#define OPTION_MEMCTLR_DR FALSE
|
||||
#define OPTION_MEMCTLR_HY FALSE
|
||||
#define OPTION_MEMCTLR_OR FALSE
|
||||
#define OPTION_MEMCTLR_C32 FALSE
|
||||
#define OPTION_MEMCTLR_DA FALSE
|
||||
#define OPTION_MEMCTLR_LN FALSE
|
||||
#define OPTION_MEMCTLR_ON FALSE
|
||||
#define OPTION_MEMCTLR_Ni FALSE
|
||||
#define OPTION_MEMCTLR_PH FALSE
|
||||
#define OPTION_MEMCTLR_RB FALSE
|
||||
|
||||
/* Default all memory controls to off */
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING FALSE
|
||||
|
@ -364,551 +169,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
#define OPTION_GFX_RECOVERY FALSE
|
||||
|
||||
/* Enable all private controls based on socket/family enables */
|
||||
#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#undef OPTION_FAMILY10H_HY
|
||||
#define OPTION_FAMILY10H_HY TRUE
|
||||
#undef OPTION_MEMCTLR_HY
|
||||
#define OPTION_MEMCTLR_HY TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_MULTISOCKET
|
||||
#define OPTION_MULTISOCKET TRUE
|
||||
#undef OPTION_SRAT
|
||||
#define OPTION_SRAT TRUE
|
||||
#undef OPTION_SLIT
|
||||
#define OPTION_SLIT TRUE
|
||||
#undef OPTION_HT_ASSIST
|
||||
#define OPTION_HT_ASSIST TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_MSG_BASED_C1E
|
||||
#define OPTION_MSG_BASED_C1E TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_RDIMMS
|
||||
#define OPTION_RDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_PARALLEL_TRAINING
|
||||
#define OPTION_PARALLEL_TRAINING TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#if (OPTION_FAMILY15H == TRUE)
|
||||
#undef OPTION_FAMILY15H_OR
|
||||
#define OPTION_FAMILY15H_OR TRUE
|
||||
#undef OPTION_MEMCTLR_OR
|
||||
#define OPTION_MEMCTLR_OR TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_CONTINOUS_PATTERN_GENERATION
|
||||
#define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
|
||||
#undef OPTION_HW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_MULTISOCKET
|
||||
#define OPTION_MULTISOCKET TRUE
|
||||
#undef OPTION_C6_STATE
|
||||
#define OPTION_C6_STATE TRUE
|
||||
#undef OPTION_IO_CSTATE
|
||||
#define OPTION_IO_CSTATE TRUE
|
||||
#undef OPTION_CPB
|
||||
#define OPTION_CPB TRUE
|
||||
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
|
||||
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
|
||||
#undef OPTION_SRAT
|
||||
#define OPTION_SRAT TRUE
|
||||
#undef OPTION_SLIT
|
||||
#define OPTION_SLIT TRUE
|
||||
#undef OPTION_HT_ASSIST
|
||||
#define OPTION_HT_ASSIST TRUE
|
||||
#undef OPTION_ATM_MODE
|
||||
#define OPTION_ATM_MODE TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_MSG_BASED_C1E
|
||||
#define OPTION_MSG_BASED_C1E TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_RDIMMS
|
||||
#define OPTION_RDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_LRDIMMS
|
||||
#define OPTION_LRDIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#undef OPTION_FAMILY10H_HY
|
||||
#define OPTION_FAMILY10H_HY TRUE
|
||||
#undef OPTION_MEMCTLR_C32
|
||||
#define OPTION_MEMCTLR_C32 TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_ADDR_TO_CS_TRANSLATOR
|
||||
#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
|
||||
#undef OPTION_MULTISOCKET
|
||||
#define OPTION_MULTISOCKET TRUE
|
||||
#undef OPTION_SRAT
|
||||
#define OPTION_SRAT TRUE
|
||||
#undef OPTION_SLIT
|
||||
#define OPTION_SLIT TRUE
|
||||
#undef OPTION_HT_ASSIST
|
||||
#define OPTION_HT_ASSIST TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_MSG_BASED_C1E
|
||||
#define OPTION_MSG_BASED_C1E TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_RDIMMS
|
||||
#define OPTION_RDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_PARALLEL_TRAINING
|
||||
#define OPTION_PARALLEL_TRAINING TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#if (OPTION_FAMILY15H == TRUE)
|
||||
#undef OPTION_FAMILY15H_OR
|
||||
#define OPTION_FAMILY15H_OR TRUE
|
||||
#undef OPTION_MEMCTLR_OR
|
||||
#define OPTION_MEMCTLR_OR TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_CONTINOUS_PATTERN_GENERATION
|
||||
#define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
|
||||
#undef OPTION_HW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_ADDR_TO_CS_TRANSLATOR
|
||||
#define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
|
||||
#undef OPTION_MULTISOCKET
|
||||
#define OPTION_MULTISOCKET TRUE
|
||||
#undef OPTION_C6_STATE
|
||||
#define OPTION_C6_STATE TRUE
|
||||
#undef OPTION_IO_CSTATE
|
||||
#define OPTION_IO_CSTATE TRUE
|
||||
#undef OPTION_CPB
|
||||
#define OPTION_CPB TRUE
|
||||
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
|
||||
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
|
||||
#undef OPTION_SRAT
|
||||
#define OPTION_SRAT TRUE
|
||||
#undef OPTION_SLIT
|
||||
#define OPTION_SLIT TRUE
|
||||
#undef OPTION_HT_ASSIST
|
||||
#define OPTION_HT_ASSIST TRUE
|
||||
#undef OPTION_ATM_MODE
|
||||
#define OPTION_ATM_MODE TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_MSG_BASED_C1E
|
||||
#define OPTION_MSG_BASED_C1E TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_RDIMMS
|
||||
#define OPTION_RDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_LRDIMMS
|
||||
#define OPTION_LRDIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#undef OPTION_FAMILY10H_BL
|
||||
#define OPTION_FAMILY10H_BL TRUE
|
||||
#undef OPTION_FAMILY10H_DA
|
||||
#define OPTION_FAMILY10H_DA TRUE
|
||||
#undef OPTION_MEMCTLR_DA
|
||||
#define OPTION_MEMCTLR_DA TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_PARALLEL_TRAINING
|
||||
#define OPTION_PARALLEL_TRAINING TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#undef OPTION_FAMILY10H_BL
|
||||
#define OPTION_FAMILY10H_BL TRUE
|
||||
#undef OPTION_FAMILY10H_DA
|
||||
#define OPTION_FAMILY10H_DA TRUE
|
||||
#undef OPTION_MEMCTLR_DA
|
||||
#define OPTION_MEMCTLR_DA TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#undef OPTION_FAMILY10H_BL
|
||||
#define OPTION_FAMILY10H_BL TRUE
|
||||
#undef OPTION_FAMILY10H_DA
|
||||
#define OPTION_FAMILY10H_DA TRUE
|
||||
#undef OPTION_MEMCTLR_Ni
|
||||
#define OPTION_MEMCTLR_Ni TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY12H == TRUE)
|
||||
#undef OPTION_FAMILY12H_LN
|
||||
#define OPTION_FAMILY12H_LN TRUE
|
||||
#undef OPTION_MEMCTLR_LN
|
||||
#define OPTION_MEMCTLR_LN TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_CONTINOUS_PATTERN_GENERATION
|
||||
#define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
|
||||
#undef OPTION_HW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_GFX_RECOVERY
|
||||
#define OPTION_GFX_RECOVERY TRUE
|
||||
#undef OPTION_C6_STATE
|
||||
#define OPTION_C6_STATE TRUE
|
||||
#undef OPTION_IO_CSTATE
|
||||
#define OPTION_IO_CSTATE TRUE
|
||||
#undef OPTION_CPB
|
||||
#define OPTION_CPB TRUE
|
||||
#undef OPTION_S3SCRIPT
|
||||
#define OPTION_S3SCRIPT TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY12H == TRUE)
|
||||
#undef OPTION_FAMILY12H_LN
|
||||
#define OPTION_FAMILY12H_LN TRUE
|
||||
#undef OPTION_MEMCTLR_LN
|
||||
#define OPTION_MEMCTLR_LN TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_CONTINOUS_PATTERN_GENERATION
|
||||
#define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
|
||||
#undef OPTION_HW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_GFX_RECOVERY
|
||||
#define OPTION_GFX_RECOVERY TRUE
|
||||
#undef OPTION_C6_STATE
|
||||
#define OPTION_C6_STATE TRUE
|
||||
#undef OPTION_IO_CSTATE
|
||||
#define OPTION_IO_CSTATE TRUE
|
||||
#undef OPTION_CPB
|
||||
#define OPTION_CPB TRUE
|
||||
#undef OPTION_S3SCRIPT
|
||||
#define OPTION_S3SCRIPT TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY12H == TRUE)
|
||||
#undef OPTION_FAMILY12H_LN
|
||||
#define OPTION_FAMILY12H_LN TRUE
|
||||
#undef OPTION_MEMCTLR_LN
|
||||
#define OPTION_MEMCTLR_LN TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_CONTINOUS_PATTERN_GENERATION
|
||||
#define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
|
||||
#undef OPTION_HW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_ADDR_TO_CS_TRANSLATOR
|
||||
#define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
|
||||
#undef OPTION_GFX_RECOVERY
|
||||
#define OPTION_GFX_RECOVERY TRUE
|
||||
#undef OPTION_C6_STATE
|
||||
#define OPTION_C6_STATE TRUE
|
||||
#undef OPTION_IO_CSTATE
|
||||
#define OPTION_IO_CSTATE TRUE
|
||||
#undef OPTION_CPB
|
||||
#define OPTION_CPB TRUE
|
||||
#undef OPTION_S3SCRIPT
|
||||
#define OPTION_S3SCRIPT TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY14H == TRUE)
|
||||
|
@ -955,128 +215,7 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
|
||||
#if (OPTION_FAMILY10H == TRUE)
|
||||
#undef OPTION_FAMILY10H_BL
|
||||
#define OPTION_FAMILY10H_BL TRUE
|
||||
#undef OPTION_FAMILY10H_DA
|
||||
#define OPTION_FAMILY10H_DA TRUE
|
||||
#undef OPTION_FAMILY10H_PH
|
||||
#define OPTION_FAMILY10H_PH TRUE
|
||||
#undef OPTION_FAMILY10H_RB
|
||||
#define OPTION_FAMILY10H_RB TRUE
|
||||
#undef OPTION_MEMCTLR_RB
|
||||
#define OPTION_MEMCTLR_RB TRUE
|
||||
#undef OPTION_MEMCTLR_DA
|
||||
#define OPTION_MEMCTLR_DA TRUE
|
||||
#undef OPTION_MEMCTLR_PH
|
||||
#define OPTION_MEMCTLR_PH TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_IO_CSTATE
|
||||
#define OPTION_IO_CSTATE TRUE
|
||||
#undef OPTION_CPB
|
||||
#define OPTION_CPB TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_PARALLEL_TRAINING
|
||||
#define OPTION_PARALLEL_TRAINING TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#if (OPTION_FAMILY15H == TRUE)
|
||||
#undef OPTION_FAMILY15H_OR
|
||||
#define OPTION_FAMILY15H_OR TRUE
|
||||
#undef OPTION_MEMCTLR_OR
|
||||
#define OPTION_MEMCTLR_OR TRUE
|
||||
#undef OPTION_HW_WRITE_LEV_TRAINING
|
||||
#define OPTION_HW_WRITE_LEV_TRAINING TRUE
|
||||
#undef OPTION_CONTINOUS_PATTERN_GENERATION
|
||||
#define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
|
||||
#undef OPTION_HW_DQS_REC_EN_TRAINING
|
||||
#define OPTION_HW_DQS_REC_EN_TRAINING TRUE
|
||||
#undef OPTION_OPT_SW_RD_WR_POS_TRAINING
|
||||
#define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
|
||||
#undef OPTION_MAX_RD_LAT_TRAINING
|
||||
#define OPTION_MAX_RD_LAT_TRAINING TRUE
|
||||
#undef OPTION_SW_DRAM_INIT
|
||||
#define OPTION_SW_DRAM_INIT TRUE
|
||||
#undef OPTION_C6_STATE
|
||||
#define OPTION_C6_STATE TRUE
|
||||
#undef OPTION_IO_CSTATE
|
||||
#define OPTION_IO_CSTATE TRUE
|
||||
#undef OPTION_CPB
|
||||
#define OPTION_CPB TRUE
|
||||
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
|
||||
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
|
||||
#undef OPTION_S3_MEM_SUPPORT
|
||||
#define OPTION_S3_MEM_SUPPORT TRUE
|
||||
#undef OPTION_ADDR_TO_CS_TRANSLATOR
|
||||
#define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
|
||||
#undef OPTION_CPU_CORELEVLING
|
||||
#define OPTION_CPU_CORELEVLING TRUE
|
||||
#undef OPTION_CPU_CFOH
|
||||
#define OPTION_CPU_CFOH TRUE
|
||||
#undef OPTION_MSG_BASED_C1E
|
||||
#define OPTION_MSG_BASED_C1E TRUE
|
||||
#undef OPTION_UDIMMS
|
||||
#define OPTION_UDIMMS TRUE
|
||||
#undef OPTION_RDIMMS
|
||||
#define OPTION_RDIMMS TRUE
|
||||
#undef OPTION_LRDIMMS
|
||||
#define OPTION_LRDIMMS TRUE
|
||||
#undef OPTION_SODIMMS
|
||||
#define OPTION_SODIMMS TRUE
|
||||
#undef OPTION_DDR3
|
||||
#define OPTION_DDR3 TRUE
|
||||
#undef OPTION_ECC
|
||||
#define OPTION_ECC TRUE
|
||||
#undef OPTION_BANK_INTERLEAVE
|
||||
#define OPTION_BANK_INTERLEAVE TRUE
|
||||
#undef OPTION_DCT_INTERLEAVE
|
||||
#define OPTION_DCT_INTERLEAVE TRUE
|
||||
#undef OPTION_NODE_INTERLEAVE
|
||||
#define OPTION_NODE_INTERLEAVE TRUE
|
||||
#undef OPTION_MEM_RESTORE
|
||||
#define OPTION_MEM_RESTORE TRUE
|
||||
#undef OPTION_ONLINE_SPARE
|
||||
#define OPTION_ONLINE_SPARE TRUE
|
||||
#undef OPTION_DIMM_EXCLUDE
|
||||
#define OPTION_DIMM_EXCLUDE TRUE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
|
||||
#if (OPTION_FAMILY14H == TRUE)
|
||||
#undef GNB_SUPPORT
|
||||
#define GNB_SUPPORT TRUE
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue