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cpu/intel/haswell: Factor out ACPI C-state values 

There's no need to have them in the devicetree. ACPI generation can now
be simplified even further, and is done in subsequent commits.

Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-28 18:50:26 +01:00 committed by Patrick Georgi
parent 6d2d19de74
commit ba5761a947
10 changed files with 26 additions and 129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

88
src/cpu/intel/haswell/acpi.c
View File

@ -14,6 +14,18 @@
#include <southbridge/intel/lynxpoint/pch.h>
static int cstate_set_lp[3] = {
2,
3,
9,
};
static int cstate_set_trad[3] = {
1,
3,
5,
};
static int get_cores_per_package(void)
{
struct cpuinfo_x86 c;
@ -30,41 +42,6 @@ static int get_cores_per_package(void)
return cores;
}
static void generate_cstate_entries(acpi_cstate_t *cstates,
int c1, int c2, int c3)
{
int cstate_count = 0;
/* Count number of active C-states */
if (c1 > 0)
++cstate_count;
if (c2 > 0)
++cstate_count;
if (c3 > 0)
++cstate_count;
if (!cstate_count)
return;
acpigen_write_package(cstate_count + 1);
acpigen_write_byte(cstate_count);
/* Add an entry if the level is enabled */
if (c1 > 0) {
cstates[c1].ctype = 1;
acpigen_write_CST_package_entry(&cstates[c1]);
}
if (c2 > 0) {
cstates[c2].ctype = 2;
acpigen_write_CST_package_entry(&cstates[c2]);
}
if (c3 > 0) {
cstates[c3].ctype = 3;
acpigen_write_CST_package_entry(&cstates[c3]);
}
acpigen_pop_len();
}
static acpi_tstate_t tss_table_fine[] = {
{ 100, 1000, 0, 0x00, 0 },
{ 94, 940, 0, 0x1f, 0 },
@ -119,18 +96,12 @@ static void generate_T_state_entries(int core, int cores_per_package)
static void generate_C_state_entries(void)
{
acpi_cstate_t map[3];
int *set;
int i;
struct cpu_info *info;
struct cpu_driver *cpu;
struct device *lapic;
struct cpu_intel_haswell_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic)
return;
conf = lapic->chip_info;
if (!conf)
return;
/* Find CPU map of supported C-states */
info = cpu_info();
@ -140,25 +111,18 @@ static void generate_C_state_entries(void)
if (!cpu || !cpu->cstates)
return;
acpigen_emit_byte(0x14); /* MethodOp */
acpigen_write_len_f(); /* PkgLength */
acpigen_emit_namestring("_CST");
acpigen_emit_byte(0x00); /* No Arguments */
if (haswell_is_ult())
set = cstate_set_lp;
else
set = cstate_set_trad;
/* If running on AC power */
acpigen_emit_byte(0xa0); /* IfOp */
acpigen_write_len_f(); /* PkgLength */
acpigen_emit_namestring("PWRS");
acpigen_emit_byte(0xa4); /* ReturnOp */
generate_cstate_entries(cpu->cstates, conf->c1_acpower,
conf->c2_acpower, conf->c3_acpower);
acpigen_pop_len();
for (i = 0; i < ARRAY_SIZE(map); i++) {
map[i] = cpu->cstates[set[i]];
map[i].ctype = i + 1;
}
/* Else on battery power */
acpigen_emit_byte(0xa4); /* ReturnOp */
generate_cstate_entries(cpu->cstates, conf->c1_battery,
conf->c2_battery, conf->c3_battery);
acpigen_pop_len();
/* Generate C-state tables */
acpigen_write_CST_package(map, ARRAY_SIZE(map));
}
static int calculate_power(int tdp, int p1_ratio, int ratio)

8
src/cpu/intel/haswell/chip.h
View File

@ -31,14 +31,6 @@ struct cpu_vr_config {
};
struct cpu_intel_haswell_config {
int c1_battery; /* ACPI C1 on Battery Power */
int c2_battery; /* ACPI C2 on Battery Power */
int c3_battery; /* ACPI C3 on Battery Power */
int c1_acpower; /* ACPI C1 on AC Power */
int c2_acpower; /* ACPI C2 on AC Power */
int c3_acpower; /* ACPI C3 on AC Power */
int tcc_offset; /* TCC Activation Offset */
struct cpu_vr_config vr_config;

7
src/mainboard/asrock/b85m_pro4/devicetree.cb
View File

@ -5,13 +5,6 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0 on end
device lapic 0xacac off end
end

7
src/mainboard/asrock/h81m-hds/devicetree.cb
View File

@ -5,13 +5,6 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0 on end
device lapic 0xacac off end
end

8
src/mainboard/google/beltino/devicetree.cb
View File

@ -18,14 +18,6 @@ chip northbridge/intel/haswell
device lapic 0 on end
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
end
end

8
src/mainboard/google/slippy/devicetree.cb
View File

@ -20,14 +20,6 @@ chip northbridge/intel/haswell
device lapic 0 on end
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
end
end

8
src/mainboard/hp/folio_9480m/devicetree.cb
View File

@ -15,14 +15,6 @@ chip northbridge/intel/haswell
register "usb_xhci_on_resume" = "true"
device cpu_cluster 0 on
chip cpu/intel/haswell
register "c1_battery" = "2"
register "c2_battery" = "3"
register "c3_battery" = "9"
register "c1_acpower" = "2"
register "c2_acpower" = "3"
register "c3_acpower" = "9"
device lapic 0 on end
device lapic 0xacac off end
end

8
src/mainboard/intel/baskingridge/devicetree.cb
View File

@ -16,14 +16,6 @@ chip northbridge/intel/haswell
device lapic 0 on end
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
register "c1_battery" = "1"
register "c2_battery" = "3"
register "c3_battery" = "5"
register "c1_acpower" = "1"
register "c2_acpower" = "3"
register "c3_acpower" = "5"
end
end

6
src/mainboard/lenovo/t440p/devicetree.cb
View File

@ -15,12 +15,6 @@ chip northbridge/intel/haswell
register "ec_present" = "true"
device cpu_cluster 0x0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end

7
src/mainboard/supermicro/x10slm-f/devicetree.cb
View File

@ -4,13 +4,6 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0 on end
device lapic 0xacac off end
end