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mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting 

Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).

BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia3813306f8c7b69fe5cf0e188c55256b68d329ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
David Wu 2021-10-25 22:52:52 +08:00 committed by Felix Held
parent 008c2b18b1
commit ba6fdc892d
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brya/variants/baseboard/brask/gpio.c
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@ -318,9 +318,9 @@ static const struct pad_config gpio_table[] = {
/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
/* R6 : I2S2_TXD ==> DMIC_CLK1_R */ /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
/* R7 : I2S2_RXD ==> DMIC_DATA1_R */ /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
/* S0 : SNDW0_CLK ==> NC */ /* S0 : SNDW0_CLK ==> NC */
PAD_NC(GPP_S0, NONE), PAD_NC(GPP_S0, NONE),