x86: Separate CPU and SoC physical address size

The physical address size of the System-on-Chip (SoC) can be different
from the CPU physical address size. These two different physical
address sizes should be used for settings of their respective field.

For instance, the physical address size related to the CPU should be
used for MTRR programming while the physical address size of the SoC
should be used for MMIO resource allocation.

Typically, on Meteor Lake, the CPUs physical address size is 46 if TME
is disabled and 42 if TME is enabled but Meteor Lake SoC physical
address size is always 42. As a result, MTRRs should reflect the TME
status while coreboot MMIO resource allocator should always use
42 bits.

This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the
physical address size of the SoC for those SoCs.

BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP

Change-Id: Icb76242718581357e5c62c2465690cf489cb1375
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/acpi/acpi_dmar.c

@@ -26,7 +26,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
 	header->length = sizeof(acpi_dmar_t);
 	header->revision = get_acpi_table_revision(DMAR);
 
-	dmar->host_address_width = cpu_phys_address_size() - 1;
+	dmar->host_address_width = soc_phys_address_size() - 1;
 	dmar->flags = flags;
 
 	current = acpi_fill_dmar(current);

src/arch/x86/Kconfig

@@ -391,4 +391,16 @@ config DUMP_SMBIOS_TYPE17
 	bool "Dump part of SMBIOS type17 dimm information"
 	depends on GENERATE_SMBIOS_TABLES
 
+config SOC_PHYSICAL_ADDRESS_WIDTH
+	int
+	default 0
+	help
+	  On some System-on-Chip the physical address size available
+	  at the SoC level may be different than at the CPU
+	  level. This configuration can be use to set the physical
+	  address width (in bits) of the SoC.
+
+	  If not set, both CPU and SoC physical address width are
+	  assume to be the same.
+
 endif

src/arch/x86/cpu_common.c

@@ -60,6 +60,14 @@ unsigned int cpu_phys_address_size(void)
 	return 32;
 }
 
+unsigned int soc_phys_address_size(void)
+{
+	if (CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH)
+		return CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH;
+
+	return cpu_phys_address_size();
+}
+
 /*
  * Get processor id using cpuid eax=1
  * return value in EAX register

src/device/pci_device.c

@@ -578,7 +578,7 @@ void pci_domain_read_resources(struct device *dev)
 	/* Initialize 64-bit memory resource constraints above 4G. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0));
 	res->base  = 4ULL * GiB;
-	res->limit = (1ULL << cpu_phys_address_size()) - 1;
+	res->limit = (1ULL << soc_phys_address_size()) - 1;
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED;
 }

src/include/cpu/cpu.h

@@ -10,6 +10,7 @@ void cpu_initialize(void);
 uintptr_t cpu_get_lapic_addr(void);
 struct bus;
 unsigned int cpu_phys_address_size(void);
+unsigned int soc_phys_address_size(void);
 
 #if ENV_RAMSTAGE
 #define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver")))

src/soc/intel/common/block/systemagent/systemagent.c

@@ -313,7 +313,7 @@ void ssdt_set_above_4g_pci(const struct device *dev)
 	uint64_t touud;
 	sa_read_map_entry(pcidev_path_on_root(SA_DEVFN_ROOT), &sa_memory_map[SA_TOUUD_REG],
 			  &touud);
-	const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud;
+	const uint64_t len = POWER_OF_2(soc_phys_address_size()) - touud;
 
 	const char *scope = acpi_device_path(dev);
 	acpigen_write_scope(scope);