soc/intel/cmn/pmc: Clear GEN_PMCON_x register power failure status bits

This patch calls into `pmc_clear_pmcon_pwr_failure_sts()` to clear
GEN_PMCON_x register status bits after determining the
`prev_sleep_state`.

Having those bits being set across reboot might be misleading.
For example: although the last boot was not due to power failure but
the power failure bit still remains the same (unless cleared).

Note: clearing `GBL_RST_STS` bit earlier than FSP-M/MRC having an
adverse effect on the PMC sleep type register which results in
calculating wrong `prev_sleep_state` post a global reset, hence,
just clearing the power failure status bits rather than clearing
the complete PMC PMCON_A register.

BUG=b:265939425
TEST=Able to clear the GEN_PMCON_A register power failure bits aka
BIT16 and BIT14 on google/marasov platform over next boot to avoid
having its persistent effect.

Without this patch:

    pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
    ...
    GEN_PMCON: d0215238 00002200

With this patch:

    pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
    ...
    GEN_PMCON: d1001038 00002200

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4f5dfe0251aeb85b667fbfc44fbf17b025aec090
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/common/block/pmc/pmclib.c

@@ -425,7 +425,13 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
 		/* Clear SLP_TYP. */
 		pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP));
 	}
-	return soc_prev_sleep_state(ps, prev_sleep_state);
+
+	prev_sleep_state = soc_prev_sleep_state(ps, prev_sleep_state);
+
+	/* Clear PMC PMCON_x register power failure status bits. */
+	pmc_clear_pmcon_pwr_failure_sts();
+
+	return prev_sleep_state;
 }
 
 void pmc_fill_pm_reg_info(struct chipset_power_state *ps)