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nb/amd/mct_ddr3: Reenable sync flood after ECC init 

The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248
and related changes have made it possible to move the sync flood enable statements
back into romstage.

Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14270
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-04-06 22:07:58 -05:00
parent e9205d537c
commit ba817d0931
2 changed files with 9 additions and 8 deletions
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8
src/northbridge/amd/amdfam10/misc_control.c
View File

@ -186,14 +186,6 @@ static void misc_control_init(struct device *dev)
/* Clear MC4 error status */
pci_write_config32(dev, 0x48, 0x0);
pci_write_config32(dev, 0x4c, 0x0);
if (mem_info->dct_stat[node].mca_config_backed_up) {
dword = pci_read_config32(dev, 0x44);
dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30;
dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21;
dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
pci_write_config32(dev, 0x44, dword);
}
}
}
#endif

9
src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
View File

@ -264,6 +264,15 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
/* Clear MC4 error status */
pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
/* Restore MCA settings */
if (pDCTstat->mca_config_backed_up) {
val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44);
val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val);
}
}
}
}