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During DRAM initialization on certain ASpeed devices, an incorrect 

bit (bit 10) was checked in the "SDRAM Bus Width Status" register
to determine DRAM width.

Query bit 6 instead in accordance with the Aspeed AST2050 datasheet
v1.05.

Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13807
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Timothy Pearson 2016-02-25 23:20:14 -06:00 committed by Martin Roth
parent d912f1d4f9
commit ba894be382
1 changed files with 1 additions and 1 deletions
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2
src/drivers/aspeed/common/ast_main.c
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@ -232,7 +232,7 @@ static int ast_get_dram_info(struct drm_device *dev)
data = ast_read32(ast, 0x10004); data = ast_read32(ast, 0x10004);
if (data & 0x400) if (data & 0x40)
ast->dram_bus_width = 16; ast->dram_bus_width = 16;
else else
ast->dram_bus_width = 32; ast->dram_bus_width = 32;