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Changed the stop_this_cpu() to just hlt. 

Removed local APIC INIT (don't worry the APIC and AP are still initialized).

The local APIC INIT seemed to be the incorrect thing to do to stop an AP.
The Intel Multiprocessor specification indicated that a vector should be set
and a START should happen following an INIT. Then AP will execute the 
instructions pointed to by the vector. There is no vector or start in
stop_this_cpu(). This seems to put the AP in an in-between state. In the case
of Barcelona the AP's MSRs and PCI register are not accessible by the hardware
debugger.

The better solution seems to be to just put the AP in a hlt and allow the AP
to go into C1. Then APIC managing software running on the BSP can program the
AP as needed.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones 2007-12-19 01:52:11 +00:00
parent 2ce8bfd251
commit ba8965c039
1 changed files with 1 additions and 16 deletions
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17
src/include/cpu/x86/lapic.h
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@ -54,22 +54,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
static inline __attribute__((always_inline)) void stop_this_cpu(void) static inline __attribute__((always_inline)) void stop_this_cpu(void)
{ {
unsigned apicid; /* Called by an AP when it is ready to halt and wait for a new task */
apicid = lapicid();
/* Send an APIC INIT to myself */
lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
lapic_write(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
/* Wait for the ipi send to finish */
lapic_wait_icr_idle();
/* Deassert the APIC INIT */
lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
lapic_write(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
/* Wait for the ipi send to finish */
lapic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) { for(;;) {
hlt(); hlt();
} }