From ba8ead817dad9be5e3afa0a702d888d4a48a640d Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Wed, 31 Oct 2018 02:26:41 +1300 Subject: [PATCH] cpu/intel/haswell: Allow use of TSC for the monotonic timer When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS with a Pentium G3258, the following exception is generated, causing the system to hang. CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000 edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90 The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located at 0x637. This MSR only exists on Haswell-ULT CPUs. So, allow boards to use the TSC monotonic timer instead. They can do this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig. Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/29383 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/Makefile.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index bbd98da10b..c317c09065 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -7,14 +7,17 @@ romstage-y += ../car/romstage.c ramstage-y += acpi.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -ramstage-y += monotonic_timer.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c + +ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) +ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c +endif cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S