mainboard/msi/ms7d25: Add NCT6687D configuration

TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors
to display information about sensors on the SIO EC.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I55445a94f0de3510324b12558c4343e819412ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2022-04-28 13:15:36 +02:00
parent f0f8a5fda8
commit ba9b2b7465
4 changed files with 47 additions and 0 deletions

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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x4e
#define NCT6687D_SHOW_SP1
#define NCT6687D_SHOW_KBC
#define NCT6687D_SHOW_EC
#include <superio/nuvoton/nct6687d/acpi/superio.asl>

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@ -11,6 +11,8 @@ void bootblock_mainboard_early_init(void)
{ {
/* Replicate vendor settings for multi-function pins in global config LDN */ /* Replicate vendor settings for multi-function pins in global config LDN */
nuvoton_pnp_enter_conf_state(SERIAL_DEV); nuvoton_pnp_enter_conf_state(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
pnp_write_config(SERIAL_DEV, 0x15, 0xaa); pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
pnp_write_config(SERIAL_DEV, 0x1a, 0x02); pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
pnp_write_config(SERIAL_DEV, 0x1b, 0x02); pnp_write_config(SERIAL_DEV, 0x1b, 0x02);

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@ -216,6 +216,37 @@ chip soc/intel/alderlake
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M2_2" "SlotDataBusWidth4X" "M2_2" "SlotDataBusWidth4X"
end end
device ref pch_espi on
chip superio/nuvoton/nct6687d
device pnp 4e.1 off end # Parallel port
device pnp 4e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.3 off end # COM2, IR
device pnp 4e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 4e.6 off end # CIR
device pnp 4e.7 off end # GPIO0-7
device pnp 4e.8 off end # P80 UART
device pnp 4e.9 off end # GPIO8-9, GPIO1-8 AF
device pnp 4e.a on # ACPI
# Vendor firmware did not assign I/O and IRQ
end
device pnp 4e.b on # EC
io 0x60 = 0xa20
# Vendor firmware did not assign IRQ
end
device pnp 4e.c off end # RTC
device pnp 4e.d off end # Deep Sleep
device pnp 4e.e off end # TACH/PWM assignment
device pnp 4e.f off end # Function register
end
end
device ref p2sb on end device ref p2sb on end
device ref hda on device ref hda on
subsystemid 0x1462 0x9d25 subsystemid 0x1462 0x9d25

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@ -24,5 +24,10 @@ DefinitionBlock(
#include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl>
} }
Scope (\_SB.PCI0.LPCB)
{
#include "acpi/superio.asl"
}
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }