arm64: Align cache maintenance code with libpayload and ARM32
coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Julius Werner
parent
3db7653aab
commit
baa3e70084
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@ -119,7 +119,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
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void cache_sync_instructions(void)
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{
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dcache_clean_all(); /* includes trailing DSB (in assembly) */
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uint32_t sctlr = raw_read_sctlr_current();
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if (sctlr & SCTLR_C)
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dcache_clean_all(); /* includes trailing DSB (assembly) */
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else if (sctlr & SCTLR_I)
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dcache_clean_invalidate_all();
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icache_invalidate_all(); /* includes leading DSB and trailing ISB */
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}
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@ -28,7 +28,6 @@ ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y)
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bootblock-y += bootblock.S
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endif
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bootblock-y += cache.c
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bootblock-y += cache_helpers.S
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bootblock-y += cpu.S
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bootblock-y += mmu.c
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@ -50,7 +49,6 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y)
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verstage-y += cache.c
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verstage-y += cpu.S
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verstage-y += cache_helpers.S
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verstage-y += exception.c
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verstage-generic-ccopts += $(armv8_flags)
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@ -63,7 +61,6 @@ endif
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ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y)
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romstage-y += cache.c
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romstage-y += cache_helpers.S
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romstage-y += cpu.S
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romstage-y += exception.c
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romstage-y += mmu.c
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@ -80,7 +77,6 @@ endif
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ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y)
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ramstage-y += cache.c
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ramstage-y += cache_helpers.S
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ramstage-y += cpu.S
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ramstage-y += exception.c
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ramstage-y += mmu.c
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@ -34,7 +34,6 @@
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#include <stdint.h>
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#include <arch/cache.h>
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#include <arch/cache_helpers.h>
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#include <arch/lib_helpers.h>
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#include <program_loading.h>
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@ -121,7 +120,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
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void cache_sync_instructions(void)
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{
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flush_dcache_all(DCCISW); /* includes trailing DSB (in assembly) */
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uint32_t sctlr = raw_read_sctlr_current();
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if (sctlr & SCTLR_C)
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dcache_clean_all(); /* includes trailing DSB (assembly) */
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else if (sctlr & SCTLR_I)
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dcache_clean_invalidate_all();
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icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */
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}
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@ -131,6 +134,10 @@ void cache_sync_instructions(void)
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*/
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void arch_segment_loaded(uintptr_t start, size_t size, int flags)
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{
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dcache_clean_invalidate_by_mva((void *)start, size);
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uint32_t sctlr = raw_read_sctlr_current();
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if (sctlr & SCTLR_C)
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dcache_clean_by_mva((void *)start, size);
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else if (sctlr & SCTLR_I)
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dcache_clean_invalidate_by_mva((void *)start, size);
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icache_invalidate_all();
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}
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@ -1,124 +0,0 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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#include <arch/cache_helpers.h>
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/* ---------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in cache_helpers.h
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* x3: The last cache level to operate on
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* x9: clidr_el1
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* and will carry out the operation on each data cache from level 0
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* to the level in x3 in sequence
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*
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* The dcsw_op macro sets up the x3 and x9 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op shift, fw, ls
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mrs x9, clidr_el1
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ubfx x3, x9, \shift, \fw
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lsl x3, x3, \ls
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b do_dcsw_op
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.endm
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ENTRY(do_dcsw_op)
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cbz x3, exit
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mov x10, xzr
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adr x14, dcsw_loop_table // compute inner loop address
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add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions
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mov x0, x9
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mov w8, #1
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loop1:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lt level_done // nothing to do if no cache or icache
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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ubfx x4, x1, #3, #10 // maximum way number
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clz w5, w4 // bit position of way size increment
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lsl w9, w4, w5 // w9 = aligned max way number
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lsl w16, w8, w5 // w16 = way number loop decrement
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orr w9, w10, w9 // w9 = combine way and cache number
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ubfx w6, w1, #13, #15 // w6 = max set number
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lsl w17, w8, w2 // w17 = set number loop decrement
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dsb sy // barrier before we start this level
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br x14 // jump to DC operation specific loop
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level_done:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.gt loop1
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msr csselr_el1, xzr // select cache level 0 in csselr
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dsb sy // barrier to complete final cache operation
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isb
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exit:
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ret
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ENDPROC(do_dcsw_op)
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.macro dcsw_loop _op
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loop2_\_op:
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lsl w7, w6, w2 // w7 = aligned max set number
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loop3_\_op:
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orr w11, w9, w7 // combine cache, way and set number
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dc \_op, x11
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subs w7, w7, w17 // decrement set number
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b.ge loop3_\_op
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subs x9, x9, x16 // decrement way number
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b.ge loop2_\_op
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b level_done
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.endm
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dcsw_loop_table:
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dcsw_loop isw
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dcsw_loop cisw
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dcsw_loop csw
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ENTRY(flush_dcache_louis)
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dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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ENDPROC(flush_dcache_louis)
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ENTRY(flush_dcache_all)
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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ENDPROC(flush_dcache_all)
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@ -1,8 +1,8 @@
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/*
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* Based on arch/arm/include/asm/cacheflush.h
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* Optimized assembly for low-level CPU operations on ARM64 processors.
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*
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* Copyright (C) 1999-2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
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* Copyright (c) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -15,11 +15,77 @@
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*/
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#include <arch/asm.h>
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#include <arch/cache_helpers.h>
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.macro dcache_apply_all crm
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dsb sy
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mrs x0, clidr_el1 // read CLIDR
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and w3, w0, #0x07000000 // narrow to LoC
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lsr w3, w3, #23 // left align LoC (low 4 bits)
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cbz w3, 5f //done
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mov w10, #0 // w10 = 2 * cache level
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mov w8, #1 // w8 = constant 0b1
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1: //next_level
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add w2, w10, w10, lsr #1 // calculate 3 * cache level
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lsr w1, w0, w2 // extract 3-bit cache type for this level
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and w1, w1, #0x7 // w1 = cache type
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cmp w1, #2 // is it data or i&d?
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b.lt 4f //skip
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msr csselr_el1, x10 // select current cache level
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isb // sync change of csselr
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mrs x1, ccsidr_el1 // w1 = read ccsidr
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and w2, w1, #7 // w2 = log2(linelen_bytes) - 4
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add w2, w2, #4 // w2 = log2(linelen_bytes)
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ubfx w4, w1, #3, #10 // w4 = associativity - 1 (also
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// max way number)
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clz w5, w4 // w5 = 32 - log2(ways)
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// (bit position of way in DC)
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lsl w9, w4, w5 // w9 = max way number
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// (aligned for DC)
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lsl w16, w8, w5 // w16 = amount to decrement (way
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// number per iteration)
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2: //next_way
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ubfx w7, w1, #13, #15 // w7 = max set #, right aligned
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lsl w7, w7, w2 // w7 = max set #, DC aligned
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lsl w17, w8, w2 // w17 = amount to decrement (set
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// number per iteration)
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3: //next_set
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orr w11, w10, w9 // w11 = combine way # & cache #
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orr w11, w11, w7 // ... and set #
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dc \crm, x11 // clean and/or invalidate line
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subs w7, w7, w17 // decrement set number
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b.ge 3b //next_set
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subs x9, x9, x16 // decrement way number
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b.ge 2b //next_way
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4: //skip
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add w10, w10, #2 // increment 2 *cache level
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cmp w3, w10 // Went beyond LoC?
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b.gt 1b //next_level
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5: //done
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dsb sy
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isb
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ret
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.endm
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ENTRY(dcache_invalidate_all)
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dcache_apply_all crm=isw
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ENDPROC(dcache_invalidate_all)
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ENTRY(dcache_clean_all)
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dcache_apply_all crm=csw
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ENDPROC(dcache_clean_all)
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ENTRY(dcache_clean_invalidate_all)
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dcache_apply_all crm=cisw
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ENDPROC(dcache_clean_invalidate_all)
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/*
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* Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a
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* known state regarding caches/SCTLR/PSTATE. Completely cleans and invalidates
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* known state regarding caches/SCTLR/PSTATE. Completely invalidates
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* icache/dcache, disables MMU and dcache (if active), and enables unaligned
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* accesses, icache and branch prediction (if inactive). Seeds the stack and
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* initializes SP_EL0. Clobbers R22 and R23.
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@ -41,9 +107,8 @@ ENTRY(arm64_init_cpu)
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msr sctlr_el3, x22
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isb
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/* Flush and invalidate dcache */
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mov x0, #DCCISW
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bl flush_dcache_all
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/* Invalidate dcache */
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bl dcache_invalidate_all
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/* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
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and x22, x22, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
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@ -37,7 +37,6 @@
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#include <arch/mmu.h>
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#include <arch/lib_helpers.h>
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#include <arch/cache.h>
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#include <arch/cache_helpers.h>
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/* This just caches the next free table slot (okay to do since they fill up from
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* bottom to top and can never be freed up again). It will reset to its initial
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@ -295,7 +294,7 @@ void mmu_enable(void)
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*/
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void mmu_disable(void)
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{
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flush_dcache_all(DCCISW);
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dcache_clean_invalidate_all();
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uint32_t sctlr = raw_read_sctlr_el3();
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sctlr &= ~(SCTLR_C | SCTLR_M);
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raw_write_sctlr_el3(sctlr);
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@ -1,47 +0,0 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
|
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CACHE_HELPERS_H
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/* CLIDR definitions */
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#define LOUIS_SHIFT 21
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#define LOC_SHIFT 24
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#define CLIDR_FIELD_WIDTH 3
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/* CSSELR definitions */
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#define LEVEL_SHIFT 1
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/* D$ set/way op type defines */
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#define DCISW 0x0
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#define DCCISW 0x1
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#define DCCSW 0x2
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#endif /* __CACHE_HELPERS_H */
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@ -67,11 +67,10 @@ void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
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/* dcache invalidate by virtual address to PoC */
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void dcache_invalidate_by_mva(void const *addr, size_t len);
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/* dcache invalidate all */
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void flush_dcache_all(int op_type);
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/* flush the dcache up to the Level of Unification Inner Shareable */
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void flush_dcache_louis(int op_type);
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/* dcache clean and/or invalidate all sets/ways to PoC */
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void dcache_clean_all(void);
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void dcache_invalidate_all(void);
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void dcache_clean_invalidate_all(void);
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/* returns number of bytes per cache line */
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unsigned int dcache_line_bytes(void);
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