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soc/intel/elkhartlake: Expose In-Band ECC config to mainboard 

Elkhart Lake provides a feature called "In-Band ECC" which uses a piece
of system DRAM to store the ECC information in. There are a few
parameters in FSP-M to set this feature up as needed.

This patch adds code to expose these parameters to the devicetree so
that they can be configured on mainboard level as needed.

Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh 2021-06-16 12:30:36 +02:00 committed by Patrick Georgi
parent 6a103907f1
commit bab5d5008b
2 changed files with 36 additions and 0 deletions
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21
src/soc/intel/elkhartlake/chip.h
View File

@ -24,6 +24,24 @@
#define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6 #define MAX_HD_AUDIO_SSP_LINKS 6
/* Define config parameters for In-Band ECC (IBECC). */
#define MAX_IBECC_REGIONS 8
enum ibecc_mode {
IBECC_PER_REGION,
IBECC_NONE,
IBECC_ALL
};
struct ehl_ibecc_config {
bool enable;
bool parity_en;
enum ibecc_mode mode;
bool region_enable[MAX_IBECC_REGIONS];
uint16_t region_base[MAX_IBECC_REGIONS];
uint16_t region_mask[MAX_IBECC_REGIONS];
};
struct soc_intel_elkhartlake_config { struct soc_intel_elkhartlake_config {
/* Common struct containing soc config data required by common code */ /* Common struct containing soc config data required by common code */
@ -68,6 +86,9 @@ struct soc_intel_elkhartlake_config {
/* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */ /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */
bool MemoryThermalThrottlingDisable; bool MemoryThermalThrottlingDisable;
/* In-Band ECC (IBECC) configuration */
struct ehl_ibecc_config ibecc;
/* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */ /* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */
bool FuSaEnable; bool FuSaEnable;

15
src/soc/intel/elkhartlake/romstage/fsp_params.c
View File

@ -107,6 +107,21 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Processor Early Power On Configuration FCLK setting */ /* Processor Early Power On Configuration FCLK setting */
m_cfg->FClkFrequency = 0x1; m_cfg->FClkFrequency = 0x1;
/* Ib-Band ECC configuration */
if (config->ibecc.enable) {
m_cfg->Ibecc = !!config->ibecc.enable;
m_cfg->IbeccParity = !!config->ibecc.parity_en;
m_cfg->IbeccOperationMode = config->ibecc.mode;
if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) {
FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionEnable,
config->ibecc.region_enable);
FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionBase,
config->ibecc.region_base);
FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionMask,
config->ibecc.region_mask);
}
}
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)