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semi working with random 1 bit error 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2006-02-28 15:39:25 +00:00
parent a51e6f1e56
commit bab9446dfd
2 changed files with 44 additions and 14 deletions
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34
src/mainboard/amd/rumba/auto.c
View File

@ -60,8 +60,36 @@ static void msr_init(void)
} }
static pll_reset(void) static void pll_reset(void)
{ {
msr_t msr;
msr = rdmsr(0x4c000014);
print_debug("CGLP_SYS_RSTPLL ");
print_debug_hex32(msr.hi);
print_debug(":");
print_debug_hex32(msr.lo);
print_debug("\n\r");
if ((msr.lo >> 26) & 0x3F) {
print_debug("reboot from BIOS reset\n\r");
return;
}
print_debug("prgramming PLL\n\r");
msr.hi = 0x00000019;
msr.lo = 0x06de0378;
wrmsr(0x4c000014, msr);
msr.lo |= ((0xde << 16) | (1 << 26));
wrmsr(0x4c000014, msr);
print_debug("Reset PLL\n\r");
msr.lo |= ((1<<14) |(1<<13) | (1<<0));
wrmsr(0x4c000014,msr);
print_debug("should not be here\n\r");
} }
static void main(unsigned long bist) static void main(unsigned long bist)
@ -76,7 +104,9 @@ static void main(unsigned long bist)
uart_init(); uart_init();
console_init(); console_init();
print_err("hi\n"); print_err("hi\n\r");
pll_reset();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
//report_bist_failure(bist); //report_bist_failure(bist);

24
src/northbridge/amd/gx2/raminit.c
View File

@ -48,15 +48,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x2000201d, msr); wrmsr(0x2000201d, msr);
print_debug("sdram_enable step 3\r\n"); print_debug("sdram_enable step 3\r\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt */
for (i = 0; i < 19; i++) {
msr = rdmsr(0x20000018);
msr.lo |= (0x01 << 3);
wrmsr(0x20000018, msr);
msr.lo &= !(0x01 << 3);
wrmsr(0x20000018, msr);
}
print_debug("sdram_enable step 4\r\n");
/* 5. set refresh interval */ /* 5. set refresh interval */
msr = rdmsr(0x20000018); msr = rdmsr(0x20000018);
@ -68,7 +59,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= !(0x03 << 6); msr.lo &= !(0x03 << 6);
wrmsr(0x20000018, msr); wrmsr(0x20000018, msr);
/* 6. enable RLL, load Extended Mode Register by set and clear PROG_DRAM */ /* 6. enable RLL, load Extended Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018); msr = rdmsr(0x20000018);
msr.lo |= ((0x01 << 28) | 0x01); msr.lo |= ((0x01 << 28) | 0x01);
@ -96,14 +86,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr); wrmsr(0x20000018, msr);
print_debug("sdram_enable step 10\r\n"); print_debug("sdram_enable step 10\r\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt */
for (i = 0; i < 19; i++) {
msr = rdmsr(0x20000018);
msr.lo |= (0x01 << 3);
wrmsr(0x20000018, msr);
msr.lo &= !(0x01 << 3);
wrmsr(0x20000018, msr);
}
print_debug("sdram_enable step 4\r\n");
/* wait 200 SDCLKs */ /* wait 200 SDCLKs */
for (i = 0; i < 200; i++) for (i = 0; i < 200; i++)
outb(0xaa, 0x80); outb(0xaa, 0x80);
/* load RDSYNC */ /* load RDSYNC */
msr = rdmsr(0x2000001a); msr = rdmsr(0x2000001f);
msr.hi = 0x000ff310; msr.hi = 0x000ff310;
wrmsr(0x20000018, msr); wrmsr(0x2000001f, msr);
print_debug("sdram_enable step 10\r\n"); print_debug("sdram_enable step 10\r\n");
/* DRAM working now?? */ /* DRAM working now?? */