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cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATION 

It was only evaluated on LEGACY_SMP_INIT path while model_106cx
has used PARALLEL_MP for a long time.

Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2022-01-29 10:22:31 +02:00 committed by Felix Held
parent d91af22f11
commit bab9d72f15
3 changed files with 1 additions and 57 deletions
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1
src/cpu/intel/model_106cx/Kconfig
View File

@ -8,6 +8,5 @@ config CPU_INTEL_MODEL_106CX
select AP_IN_SIPI_WAIT select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select SERIALIZED_SMM_INITIALIZATION
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE select CPU_INTEL_COMMON_TIMEBASE

11
src/cpu/x86/Kconfig
View File

@ -147,17 +147,6 @@ config SMM_LAPIC_REMAP_MITIGATION
default y if NORTHBRIDGE_INTEL_IRONLAKE default y if NORTHBRIDGE_INTEL_IRONLAKE
default n default n
config SERIALIZED_SMM_INITIALIZATION
bool
default n
help
On some CPUs, there is a race condition in SMM.
This can occur when both hyperthreads change SMM state
variables in parallel without coordination.
Setting this option serializes the SMM initialization
to avoid an ugly hang in the boot process at the cost
of a slightly longer boot time.
config X86_AMD_FIXED_MTRRS config X86_AMD_FIXED_MTRRS
bool bool
default n default n

46
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -332,37 +332,6 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
} }
static void smm_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
{
struct device *cpu;
int pre_count = atomic_read(&active_cpus);
/* Loop through the cpus once to let them run through SMM relocator */
for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC)
continue;
printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n",
cpu->path.apic.apic_id);
if (cpu == bsp_cpu)
continue;
if (!cpu->enabled)
continue;
if (!start_cpu(cpu))
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
/* FIXME: endless loop */
while (atomic_read(&active_cpus) != pre_count)
;
}
}
static void wait_other_cpus_stop(struct bus *cpu_bus) static void wait_other_cpus_stop(struct bus *cpu_bus)
{ {
struct device *cpu; struct device *cpu;
@ -422,8 +391,7 @@ void initialize_cpus(struct bus *cpu_bus)
if (is_smp_boot()) if (is_smp_boot())
copy_secondary_start_to_lowest_1M(); copy_secondary_start_to_lowest_1M();
if (!CONFIG(SERIALIZED_SMM_INITIALIZATION)) smm_init();
smm_init();
/* Initialize the bootstrap processor */ /* Initialize the bootstrap processor */
cpu_initialize(0); cpu_initialize(0);
@ -435,18 +403,6 @@ void initialize_cpus(struct bus *cpu_bus)
if (is_smp_boot()) if (is_smp_boot())
wait_other_cpus_stop(cpu_bus); wait_other_cpus_stop(cpu_bus);
if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) {
/* At this point, all APs are sleeping:
* smm_init() will queue a pending SMI on all cpus
* and smm_other_cpus() will start them one by one */
smm_init();
if (is_smp_boot()) {
last_cpu_index = 0;
smm_other_cpus(cpu_bus, info->cpu);
}
}
smm_init_completion(); smm_init_completion();
if (is_smp_boot()) if (is_smp_boot())