mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) support

Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11954
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

src/mainboard/asus/kgpe-d16/Kconfig

@@ -23,6 +23,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select ENABLE_APIC_EXT_ID
 	select MMCONF_SUPPORT_DEFAULT
+	select SPI_FLASH
+	select SPI_FLASH_WINBOND
+	select HAVE_ACPI_RESUME
 	select DRIVERS_I2C_W83795
 	select DRIVERS_ASPEED_AST2050
 	select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG

src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl

@@ -14,28 +14,24 @@
  * GNU General Public License for more details.
  */
 
-/*
+/* Port 80 POST card debug */
- * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
+OperationRegion (DBG0, SystemIO, 0x80, One)
- */
-
-	/* Port 80 POST card debug */
-	OperationRegion (DBG0, SystemIO, 0x80, One)
 	Field (DBG0, ByteAcc, NoLock, Preserve) {
 	DBG8, 8
-	}
+}
 
-	/* SuperIO control port */
+/* SuperIO control port */
-	Name (SPIO, 0x2E)
+Name (SPIO, 0x2E)
 
-	/* SuperIO control map */
+/* SuperIO control map */
-	OperationRegion (SPIM, SystemIO, SPIO, 0x02)
+OperationRegion (SPIM, SystemIO, SPIO, 0x02)
 	Field (SPIM, ByteAcc, NoLock, Preserve) {
 	INDX, 8,
 	DATA, 8
-	}
+}
 
-	/* SuperIO control registers */
+/* SuperIO control registers */
-	IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
+IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
 	Offset (0x07),
 	CR07, 8,		/* Logical device number */
 	Offset (0x2C),
@@ -44,6 +40,8 @@
 	CR30, 8,		/* Logical device activation control register */
 	Offset (0xE0),
 	CRE0, 8,		/* Wake control register */
+	Offset (0xE4),
+	CRE4, 8,		/* Standby power control register */
 	Offset (0xE6),
 	CRE6, 8,		/* Mouse wake event configuration register */
 	Offset (0xF1),
@@ -54,15 +52,15 @@
 	CRF6, 8,		/* SMI/PME event generation control register */
 	Offset (0xF9),
 	CRF9, 8,		/* ACPI PME configuration register */
-	}
+}
 
-	/* Power Management I/O registers */
+/* Power Management I/O registers */
-	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
 	Field(PIOR, ByteAcc, NoLock, Preserve) {
 	PIOI, 0x00000008,
 	PIOD, 0x00000008,
-	}
+}
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 	Offset(0x00),	/* MiscControl */
 	, 1,
 	T1EE, 1,
@@ -138,8 +136,11 @@
 	Offset(0x65),	/* UsbPMControl */
 	, 4,
 	URRE, 1,
+	, 2,
+	BCDL, 1,
 	Offset(0x68),	/* MiscEnable68 */
-		, 3,
+	, 2,
+	MAPC, 1,
 	TMTE, 1,
 	, 1,
 	Offset(0x7C),	/* MiscEnable7C */
@@ -164,12 +165,12 @@
 	IO5S, 1,
 	IO6S, 1,
 	IO7S, 1,
-	}
+}
 
-	/* PM1 Event Block
+/* PM1 Event Block
 	* First word is PM1_Status, Second word is PM1_Enable
 	*/
-	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+OperationRegion(P1EB, SystemIO, APEB, 0x04)
 	Field(P1EB, ByteAcc, NoLock, Preserve) {
 	TMST, 1,
 	,    3,
@@ -192,12 +193,12 @@
 	RTEN, 1,
 	, 3,
 	PWDA, 1,
-	}
+}
 
-	/* Wake status package */
+/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
+Name(WKST,Package() {Zero, Zero})
 
-	/*
+/*
  *  \_WAK System Wake method
  *
  *	Entry:
@@ -212,7 +213,7 @@
  *		Dword 2 - Power Supply state
  *			if non-zero the effective S-state the power supply entered
  */
-	Method(\_WAK, 1) {
+Method(\_WAK, 1) {
 	Store (0x20, DBG8)
 
 	/* Set up LEDs */
@@ -262,9 +263,9 @@
 	Notify(\_SB.PWRB, 0x02)			/* NOTIFY_DEVICE_WAKE */
 
 	Return(WKST)
-	}
+}
 
-	/*
+/*
  * \_PTS - Prepare to Sleep method
  *
  *	Entry:
@@ -280,7 +281,7 @@
  * the ACPI driver.  This method cannot modify the configuration or power
  * state of any device in the system.
  */
-	Method(\_PTS, 1) {
+Method(\_PTS, 1) {
 	Store (Arg0, DBG8)
 
 	/* Set up LEDs */
@@ -313,6 +314,7 @@
 			* LPT
 			* FDC
 			* UART
+			*/
 		Store(0x00, CRF6)
 
 		/* Enable PS/2 keyboard SMI/PME events */
@@ -333,6 +335,12 @@
 		/* Enable PS/2 mouse wake on any click  */
 		Or(CRE0, 0x22, CRE0)
 		Or(CRE6, 0x80, CRE6)
+
+		if (LEqual(Arg0, 0x03))	/* Power state S3 requested */
+		{
+			/* Set VSBGATE# to provide standby power during S3 */
+			Or(CRE4, 0x10, CRE4)
+		}
 	}
 
 	/* Restore default SuperIO access */
@@ -346,9 +354,10 @@
 	}
 
 	/* Configure southbridge for sleep */
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+	/* Use bus clock for delay timebase */
-		// Store(One, CSSM)	/* Set ExtEvent0 as SMI# source */
+	Store(0, BCDL)
-		// Store(One, SSEN)	/* Enable wake on external event 0 */
+	/* Defer APIC interrupts until first ACPI access */
+	Store(One, MAPC)
 
 	/* On older chips, clear PciExpWakeDisEn */
 	// if (LLessEqual(SBRI, 0x13)) {
@@ -360,4 +369,4 @@
 	/* Clear wake status structure. */
 	Store(0, Index(WKST,0))
 	Store(0, Index(WKST,1))
-	}
+}

src/mainboard/asus/kgpe-d16/dsdt.asl

@@ -54,9 +54,8 @@ DefinitionBlock (
 	/* Define power states */
 	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })	/* Normal operation */
 	Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 })	/* Standby */
-	Name (\_S2, Package () { 0x02, 0x02, 0x00, 0x00 })	/* Standby w/ CPU shutdown */
+	Name (\_S3, Package () { 0x03, 0x03, 0x00, 0x00 })	/* Suspend to RAM */
-	Name (\_S3, Package () { 0x03, 0x00, 0x00, 0x00 })	/* Suspend */
+	Name (\_S4, Package () { 0x04, 0x04, 0x00, 0x00 })	/* Suspend to disk */
-	/* Name (\_S4, Package () { 0x04, 0x04, 0x00, 0x00 }) */
 	Name (\_S5, Package () { 0x05, 0x05, 0x00, 0x00 })	/* Hard power off */
 
 	/* The _PIC method is called by the OS to choose between interrupt

src/mainboard/asus/kgpe-d16/romstage.c

@@ -220,12 +220,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sys_info *sysinfo = &sysinfo_car;
 
-	u32 bsp_apicid = 0, val;
+	uint32_t bsp_apicid = 0, val;
+	uint8_t byte;
 	msr_t msr;
 
 	timestamp_init(timestamp_get());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
+	int s3resume = acpi_is_wakeup_s3();
+
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
@@ -243,6 +246,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* Initialize early serial */
 		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		console_init();
+
+		/* Disable LPC legacy DMA support to prevent lockup */
+		byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0x78);
+		byte &= ~(1 << 0);
+		pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte);
 	}
 
 	post_code(0x30);
@@ -281,14 +289,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	amd_ht_fixup(sysinfo);
 	post_code(0x35);
 
-	/* Set DDR memory voltage
-	 * FIXME
-	 * This should be set based on the output of the DIMM SPDs
-	 * For now it is locked to 1.5V
-	 */
-	set_ddr3_voltage(0, 0);	/* Node 0 */
-	set_ddr3_voltage(1, 0);	/* Node 1 */
-
 	/* Setup nodes PCI space and start core 0 AP init. */
 	finalize_node_setup(sysinfo);
 
@@ -351,6 +351,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		die("After soft_reset_x - shouldn't see this message!!!\n");
 	}
 
+	/* Set DDR memory voltage
+	 * FIXME
+	 * This should be set based on the output of the DIMM SPDs
+	 * For now it is locked to 1.5V
+	 */
+	set_lpc_sticky_ctl(1);	/* Retain LPC/IMC GPIO configuration during S3 sleep */
+	if (!s3resume) {	/* Avoid supply voltage glitches while the DIMMs are retaining data */
+		set_ddr3_voltage(0, 0);	/* Node 0 */
+		set_ddr3_voltage(1, 0);	/* Node 1 */
+	}
+
 	/* Set up peripheral control lines */
 	set_peripheral_control_lines();
 
@@ -380,6 +391,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	timestamp_add_now(TS_AFTER_INITRAM);
 
 #if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+	if (s3resume)
+		cbmem_initialize();
+	else
 		cbmem_initialize_empty();
 	post_code(0x41);
 

src/mainboard/asus/kgpe-d16/spd_notes.txt

@@ -28,3 +28,19 @@ Other hardware
 
 RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61
 Normal is HIGH, recovery is LOW.
+
++12VSB is generated using a charge pump attached to pin 7 of PU24 (APW7145).
+
+The +12VSB standby voltage to each bank of DIMMs is switched by a bank of small FETs located close to each RAM power regulator control chip.
+The +12V primary voltage (lower left pin of the FET placed on the upper left of the control chip of the second node) is also connected to the 232GE located near the PCI slot.
+
+The control line running to the gates of the +12VSB control FETs is connected to the +5VSB power for the USB ports.
+That line in turn is connected to +5VSB via the lone P06P03G PMOS transistor on the reverse side of the board, near the center on the lower half.
+The gate of that transistor is connected via a resistor to the source of the P06P03G PMOS transistor located adjacent to the unpopulated SMA clock header.
+The gate of that transistor is connected directly to the drain of the small FET directly below it.
+After that, there's a cascade of small FETs and resistors in that region, eventually leading to SuperIO pin 81.
+
+SuperIO pin 81 (VSBGATE#) enables the standby voltage rails when set LOW.
+VSBGATE# is reset on every assertion of PWRGOOD.
+
+Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB.