From bad64c8b9b8ac4f5b17486ef735731be95a531a4 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 15 Dec 2021 00:30:10 +0100 Subject: [PATCH] soc/amd/cezanne/fch: disable 48MHz output in S0i3 S0i3 is a low power state which reduces the power consumption to about the level of the S3 suspend state where the DRAM is kept in a self- refresh state and most of the rest of the system is powered down. So everything that can be switched off in the S0i3 state should be switched off in order to maximize the standby time. BUG=b:210722314 Signed-off-by: Felix Held Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125 Tested-by: build bot (Jenkins) Reviewed-by: Jason Glenesk Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/fch.c | 2 ++ src/soc/amd/cezanne/include/soc/southbridge.h | 1 + 2 files changed, 3 insertions(+) diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 8cd1212420..2c57f08d96 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -78,6 +78,8 @@ static void fch_clk_output_48Mhz(void) uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); /* Enable BP_X48M0 Clock Output */ ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ + ctrl |= BP_X48M0_S0I3_DIS; misc_write32(MISC_CLK_CNTL0, ctrl); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 3bba559f8f..4f372adf94 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -110,6 +110,7 @@ #define USB_PHY_CMCLK_S0I3_DIS BIT(9) #define USB_PHY_CMCLK_S5_DIS BIT(10) #define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ +#define BP_X48M0_S0I3_DIS BIT(4) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define MISC_I2C0_PAD_CTRL 0xd8 #define MISC_I2C1_PAD_CTRL 0xdc