mb/intel/coffeelake_rvp: Update GPIO table for Coffeelake U RVP
Update GPIO table as per board schematics. GPIO table for other variants will be added later. Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This commit is contained in:
Maulik V Vaghela
Patrick Georgi
parent
9b56ef05cc
commit
bad8fbb22c
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@ -16,9 +16,8 @@
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <compiler.h>
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/* Pad configuration in ramstage*/
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#if IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)
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static const struct pad_config gpio_table[] = {
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/* GPPC */
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/* A0 : RCINB_TIME_SYNC_1 */
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@ -43,14 +42,14 @@ static const struct pad_config gpio_table[] = {
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/* A15 : SUSACKB */
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PAD_CFG_GPO(GPP_A15, 1, PLTRST),
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/* A16 : SD_1P8_SEL */
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PAD_CFG_GPO(GPP_A16, 0, PLTRST),
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PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST),
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/* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */
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/* A18 : ISH_GP_0 */
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PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),
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/* A19 : ISH_GP_1 */
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PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),
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/* A20 : aduio codec irq */
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PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),
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/* A20 : ISH_GP_2 */
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PAD_CFG_NF(GPP_A20, UP_20K, DEEP, NF1),
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/* A21 : ISH_GP_3 */
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PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),
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/* A22 : ISH_GP_4 */
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@ -110,7 +109,7 @@ static const struct pad_config gpio_table[] = {
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/* C10 : UART0_RTSB */
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PAD_CFG_GPO(GPP_C10, 0, PLTRST),
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/* C11 : UART0_CTSB */
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PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL),
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PAD_CFG_TERM_GPO(GPP_C11, 1, UP_20K, DEEP),
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/* C12 : UART1_RXD_ISH_UART1_RXD */
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PAD_CFG_GPO(GPP_C12, 1, PLTRST),
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/* C13 : UART1_RXD_ISH_UART1_TXD */
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@ -138,7 +137,7 @@ static const struct pad_config gpio_table[] = {
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/* D9 : ISH_SPI_CSB */
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PAD_CFG_GPO(GPP_D9, 1, PLTRST),
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/* D10 : ISH_SPI_CLK */
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PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE),
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PAD_CFG_GPI_APIC(GPP_D10, UP_20K, PLTRST, LEVEL, INVERT),
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/* D11 : ISH_SPI_MISO_GP_BSSB_CLK */
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PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),
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/* D12 : ISH_SPI_MOSI_GP_BSSB_DI */
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@ -150,23 +149,15 @@ static const struct pad_config gpio_table[] = {
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/* D16 : ISH_UART0_CTSB_SML0BALERTB */
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PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),
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/* D17 : DMIC_CLK_1_SNDW3_CLK */
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PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
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/* D18 : DMIC_DATA_1_SNDW3_DATA */
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PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
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/* D19 : DMIC_CLK_0_SNDW4_CLK */
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PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
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/* D20 : DMIC_DATA_0_SNDW4_DATA */
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PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
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/* D21 : SPI1_IO_2 */
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PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),
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/* D22 : SPI1_IO_3 */
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PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),
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/* D23 : SPP_MCLK */
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PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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/* E0 : SATAXPCIE_0_SATAGP_0 */
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#if IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVP11)
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PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
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#endif
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/* E1 : SATAXPCIE_1_SATAGP_1 */
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/* E2 : SATAXPCIE_2_SATAGP_2 */
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PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),
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@ -247,9 +238,7 @@ static const struct pad_config gpio_table[] = {
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/* H4 : I2C2_SDA */
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/* H5 : I2C2_SCL */
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/* H6 : I2C3_SDA */
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PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),
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/* H7 : I2C3_SCL */
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PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),
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/* H8 : I2C4_SDA */
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/* H9 : I2C4_SCL */
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/* H10 : I2C5_SDA_ISH_I2C2_SDA */
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@ -261,7 +250,7 @@ static const struct pad_config gpio_table[] = {
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/* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */
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PAD_CFG_GPO(GPP_H13, 1, PLTRST),
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/* H14 : M2_SKT2_CFG_2 */
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PAD_CFG_GPO(GPP_H14, 0, PLTRST),
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PAD_CFG_GPO(GPP_H14, 1, PLTRST),
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/* H15 : M2_SKT2_CFG_3 */
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PAD_CFG_GPO(GPP_H15, 1, PLTRST),
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/* H16 : CAM5_PWR_EN */
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@ -274,7 +263,7 @@ static const struct pad_config gpio_table[] = {
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/* H20 : IMGCLKOUT_1 */
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/* H21 : GPPC_H_21 */
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/* H22 : GPPC_H_22 */
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PAD_CFG_GPO(GPP_H22, 1, PLTRST),
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PAD_CFG_GPI(GPP_H22, NONE, DEEP),
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/* H23 : GPPC_H_23 */
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/* GPD */
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@ -290,7 +279,14 @@ static const struct pad_config gpio_table[] = {
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/* GPD-9 : SLP_WLANB */
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/* GPD-10 : SLP_5B */
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/* GPD_11 : LANPHYPC */
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};
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#elif IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVP11)
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static const struct pad_config gpio_table[] = {
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};
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#endif
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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@ -304,8 +300,7 @@ const struct pad_config *__weak variant_gpio_table(size_t *num)
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return gpio_table;
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}
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const struct pad_config *__weak
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variant_early_gpio_table(size_t *num)
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const struct pad_config *__weak variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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@ -315,7 +310,7 @@ static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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};
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const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
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const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
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{
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*num = ARRAY_SIZE(cros_gpios);
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return cros_gpios;
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