GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/mediatek/mt8186: add SPM loader 

This patch adds support for loading SPM firmware from CBFS to SPM SRAM.
SPM needs its own firmware to enable SPM suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59341
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rex-BC Chen 2021-11-10 20:42:40 +08:00 committed by Hung-Te Lin
parent d8e8c873c0
commit bade5caedb
4 changed files with 1019 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/mediatek/mt8186/Kconfig
View File

@ -16,6 +16,12 @@ config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_RETURN_FROM_VERSTAGE
config SPM_FIRMWARE
string
default "spm_firmware.bin"
help
The file name of the MediaTek SPM firmware.
config SSPM_FIRMWARE
string
default "sspm.bin"

4
src/soc/mediatek/mt8186/Makefile.inc
View File

@ -46,6 +46,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += soc.c
ramstage-y += ../common/spm.c spm.c
ramstage-y += ../common/sspm.c
ramstage-y += ../common/timer.c timer.c
ramstage-y += ../common/uart.c
@ -59,7 +60,8 @@ CPPFLAGS_common += -Isrc/soc/mediatek/common/include
MT8186_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8186
mcu-firmware-files := \
$(CONFIG_SSPM_FIRMWARE)
$(CONFIG_SSPM_FIRMWARE) \
$(CONFIG_SPM_FIRMWARE)
$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \
$(eval $(fw)-file := $(MT8186_BLOB_DIR)/$(fw)) \

325
src/soc/mediatek/mt8186/include/soc/spm.h
View File

@ -8,9 +8,137 @@
#ifndef SOC_MEDIATEK_MT8186_SPM_H
#define SOC_MEDIATEK_MT8186_SPM_H
#include <device/mmio.h>
#include <soc/addressmap.h>
#include <types.h>
#define SPM_INIT_DONE_US 20
#define CLK_SCP_CFG_0 (IO_PHYS + 0x200)
#define CLK_SCP_CFG_1 (IO_PHYS + 0x210)
#define INFRA_AO_RES_CTRL_MASK (INFRACFG_AO_BASE + 0xB8)
#define AP_PLL_CON3 (APMIXED_BASE + 0xC)
#define AP_PLL_CON4 (APMIXED_BASE + 0x10)
/* MD32PCM ADDR for SPM code fetch */
#define MD32PCM_BASE (SPM_BASE + 0x0A00)
#define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
#define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
#define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
#define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
#define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
#define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
#define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
#define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
#define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
#define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C)
#define MD32PCM_CFGREG_SW_RSTN_RUN 1
#define MD32PCM_DMA0_CON_VAL 0x0003820E
#define MD32PCM_DMA0_START_VAL 0x00008000
/* SPM */
#define BCLK_CG_EN_LSB BIT(0)
#define PCM_CK_EN_LSB BIT(2)
#define PCM_SW_RESET_LSB BIT(15)
#define RG_AHBMIF_APBEN_LSB BIT(3)
#define REG_MD32_APB_INTERNAL_EN_LSB BIT(14)
#define PCM_RF_SYNC_R7 BIT(23)
#define REG_DDREN_DBC_EN_LSB BIT(16)
DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0)
DEFINE_BIT(REG_SYSCLK1_SRC_MD2_SRCCLKENA, 28)
DEFINE_BIT(SPM_ACK_CHK_3_CON_CLR_ALL, 1)
DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4)
DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8)
DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 9)
DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 10)
DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 18)
DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 15)
DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2)
DEFINE_BIT(SPM_DVFSRC_ENABLE_LSB, 4)
DEFINE_BIT(SYS_TIMER_START_EN_LSB, 0)
#define SPM_PROJECT_CODE 0xB16
#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
#define POWER_ON_VAL1_DEF 0x80015860
#define SPM_WAKEUP_EVENT_MASK_DEF 0xEFFFFFFF
#define DDREN_DBC_EN_VAL 0x154
#define ARMPLL_CLK_SEL_DEF 0x3FF
#define SPM_RESOURCE_ACK_CON0_DEF 0x00000000
#define SPM_RESOURCE_ACK_CON1_DEF 0x00000000
#define SPM_RESOURCE_ACK_CON2_DEF 0xCCCC4E4E
#define SPM_RESOURCE_ACK_CON3_DEF 0x00000000
#define APMIX_CON3_DEF 0xFFFF7770
#define APMIX_CON4_DEF 0xFFFAA007
#define SCP_CFG0_DEF 0x3FF
#define SCP_CFG1_DEF 0x3
#define SPM_DVFS_LEVEL_DEF 0x00000001
#define SPM_DVS_DFS_LEVEL_DEF 0x00010001
#define SPM_ACK_CHK_3_SEL_HW_S1 0x0035009F
#define SPM_ACK_CHK_3_HW_S1_CNT 1
#define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */
#define SPM_WAKEUP_EVENT_MASK_BIT0 1
#define RG_PCM_TIMER_EN_LSB BIT(5)
#define RG_PCM_WDT_WAKE_LSB BIT(9)
#define PCM_RF_SYNC_R0 BIT(16)
#define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(6)
#define R12_CSYSPWREQ_B BIT(24)
#define SPM_BUS_PROTECT_MASK_B_DEF 0xFFFFFFFF
#define SPM_BUS_PROTECT2_MASK_B_DEF 0xFFFFFFFF
#define SPM_FLAG_DISABLE_VCORE_DVS BIT(3)
#define SPM_FLAG_DISABLE_VCORE_DFS BIT(4)
#define SPM_FLAG_RUN_COMMON_SCENARIO BIT(10)
/* PCM_WDT_VAL */
#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
/* PCM_TIMER_VAL */
#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
/* SPM_IRQ_MASK */
#define ISRM_TWAM BIT(2)
#define ISRM_PCM_RETURN BIT(3)
#define ISRM_RET_IRQ0 BIT(8)
#define ISRM_RET_IRQ1 BIT(9)
#define ISRM_RET_IRQ2 BIT(10)
#define ISRM_RET_IRQ3 BIT(11)
#define ISRM_RET_IRQ4 BIT(12)
#define ISRM_RET_IRQ5 BIT(13)
#define ISRM_RET_IRQ6 BIT(14)
#define ISRM_RET_IRQ7 BIT(15)
#define ISRM_RET_IRQ8 BIT(16)
#define ISRM_RET_IRQ9 BIT(17)
#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | ISRM_RET_IRQ7 | \
ISRM_RET_IRQ6 | ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \
ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | ISRM_RET_IRQ1)
#define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX
#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
/* SPM_IRQ_STA */
#define ISRS_TWAM BIT(2)
#define ISRS_PCM_RETURN BIT(3)
#define ISRC_TWAM ISRS_TWAM
#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
/* SPM_SWINT */
#define PCM_SW_INT0 BIT(0)
#define PCM_SW_INT1 BIT(1)
#define PCM_SW_INT2 BIT(2)
#define PCM_SW_INT3 BIT(3)
#define PCM_SW_INT4 BIT(4)
#define PCM_SW_INT5 BIT(5)
#define PCM_SW_INT6 BIT(6)
#define PCM_SW_INT7 BIT(7)
#define PCM_SW_INT8 BIT(8)
#define PCM_SW_INT9 BIT(9)
#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
PCM_SW_INT0)
struct mtk_spm_regs {
uint32_t poweron_config_en;
uint32_t spm_power_on_val0;
@ -522,12 +650,209 @@ struct mtk_spm_regs {
uint32_t adsp_ao_pwr_con;
};
struct pwr_ctrl {
/* For SPM */
uint32_t pcm_flags;
uint32_t pcm_flags_cust;
uint32_t pcm_flags_cust_set;
uint32_t pcm_flags_cust_clr;
uint32_t pcm_flags1;
uint32_t pcm_flags1_cust;
uint32_t pcm_flags1_cust_set;
uint32_t pcm_flags1_cust_clr;
uint32_t timer_val;
uint32_t timer_val_cust;
uint32_t timer_val_ramp_en;
uint32_t timer_val_ramp_en_sec;
uint32_t wake_src;
uint32_t wake_src_cust;
uint32_t wakelock_timer_val;
uint8_t wdt_disable;
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
uint8_t reg_wfi_op;
uint8_t reg_wfi_type;
uint8_t reg_mp0_cputop_idle_mask;
uint8_t reg_mp1_cputop_idle_mask;
uint8_t reg_mcusys_idle_mask;
uint8_t reg_md_apsrc_1_sel;
uint8_t reg_md_apsrc_0_sel;
uint8_t reg_conn_apsrc_sel;
/* SPM_SRC6_MASK */
uint32_t reg_ccif_event_infra_req_mask_b;
uint32_t reg_ccif_event_apsrc_req_mask_b;
/* SPM_SRC_REQ */
uint8_t reg_spm_apsrc_req;
uint8_t reg_spm_f26m_req;
uint8_t reg_spm_infra_req;
uint8_t reg_spm_vrf18_req;
uint8_t reg_spm_ddren_req;
uint8_t reg_spm_dvfs_req;
uint8_t reg_spm_sw_mailbox_req;
uint8_t reg_spm_sspm_mailbox_req;
uint8_t reg_spm_adsp_mailbox_req;
uint8_t reg_spm_scp_mailbox_req;
/* SPM_SRC_MASK */
uint8_t reg_md_0_srcclkena_mask_b;
uint8_t reg_md_0_infra_req_mask_b;
uint8_t reg_md_0_apsrc_req_mask_b;
uint8_t reg_md_0_vrf18_req_mask_b;
uint8_t reg_md_0_ddren_req_mask_b;
uint8_t reg_md_1_srcclkena_mask_b;
uint8_t reg_md_1_infra_req_mask_b;
uint8_t reg_md_1_apsrc_req_mask_b;
uint8_t reg_md_1_vrf18_req_mask_b;
uint8_t reg_md_1_ddren_req_mask_b;
uint8_t reg_conn_srcclkena_mask_b;
uint8_t reg_conn_srcclkenb_mask_b;
uint8_t reg_conn_infra_req_mask_b;
uint8_t reg_conn_apsrc_req_mask_b;
uint8_t reg_conn_vrf18_req_mask_b;
uint8_t reg_conn_ddren_req_mask_b;
uint8_t reg_conn_vfe28_mask_b;
uint8_t reg_srcclkeni_srcclkena_mask_b;
uint8_t reg_srcclkeni_infra_req_mask_b;
uint8_t reg_infrasys_apsrc_req_mask_b;
uint8_t reg_infrasys_ddren_req_mask_b;
uint8_t reg_sspm_srcclkena_mask_b;
uint8_t reg_sspm_infra_req_mask_b;
uint8_t reg_sspm_apsrc_req_mask_b;
uint8_t reg_sspm_vrf18_req_mask_b;
uint8_t reg_sspm_ddren_req_mask_b;
/* SPM_SRC2_MASK */
uint8_t reg_scp_srcclkena_mask_b;
uint8_t reg_scp_infra_req_mask_b;
uint8_t reg_scp_apsrc_req_mask_b;
uint8_t reg_scp_vrf18_req_mask_b;
uint8_t reg_scp_ddren_req_mask_b;
uint8_t reg_audio_dsp_srcclkena_mask_b;
uint8_t reg_audio_dsp_infra_req_mask_b;
uint8_t reg_audio_dsp_apsrc_req_mask_b;
uint8_t reg_audio_dsp_vrf18_req_mask_b;
uint8_t reg_audio_dsp_ddren_req_mask_b;
uint8_t reg_ufs_srcclkena_mask_b;
uint8_t reg_ufs_infra_req_mask_b;
uint8_t reg_ufs_apsrc_req_mask_b;
uint8_t reg_ufs_vrf18_req_mask_b;
uint8_t reg_ufs_ddren_req_mask_b;
uint8_t reg_disp0_apsrc_req_mask_b;
uint8_t reg_disp0_ddren_req_mask_b;
uint8_t reg_disp1_apsrc_req_mask_b;
uint8_t reg_disp1_ddren_req_mask_b;
uint8_t reg_gce_infra_req_mask_b;
uint8_t reg_gce_apsrc_req_mask_b;
uint8_t reg_gce_vrf18_req_mask_b;
uint8_t reg_gce_ddren_req_mask_b;
uint8_t reg_apu_srcclkena_mask_b;
uint8_t reg_apu_infra_req_mask_b;
uint8_t reg_apu_apsrc_req_mask_b;
uint8_t reg_apu_vrf18_req_mask_b;
uint8_t reg_apu_ddren_req_mask_b;
uint8_t reg_cg_check_srcclkena_mask_b;
uint8_t reg_cg_check_apsrc_req_mask_b;
uint8_t reg_cg_check_vrf18_req_mask_b;
uint8_t reg_cg_check_ddren_req_mask_b;
/* SPM_SRC3_MASK */
uint8_t reg_dvfsrc_event_trigger_mask_b;
uint8_t reg_sw2spm_wakeup_mask_b;
uint8_t reg_adsp2spm_wakeup_mask_b;
uint8_t reg_sspm2spm_wakeup_mask_b;
uint8_t reg_scp2spm_wakeup_mask_b;
uint8_t reg_csyspwrup_ack_mask;
uint8_t reg_spm_reserved_srcclkena_mask_b;
uint8_t reg_spm_reserved_infra_req_mask_b;
uint8_t reg_spm_reserved_apsrc_req_mask_b;
uint8_t reg_spm_reserved_vrf18_req_mask_b;
uint8_t reg_spm_reserved_ddren_req_mask_b;
uint8_t reg_mcupm_srcclkena_mask_b;
uint8_t reg_mcupm_infra_req_mask_b;
uint8_t reg_mcupm_apsrc_req_mask_b;
uint8_t reg_mcupm_vrf18_req_mask_b;
uint8_t reg_mcupm_ddren_req_mask_b;
uint8_t reg_msdc0_srcclkena_mask_b;
uint8_t reg_msdc0_infra_req_mask_b;
uint8_t reg_msdc0_apsrc_req_mask_b;
uint8_t reg_msdc0_vrf18_req_mask_b;
uint8_t reg_msdc0_ddren_req_mask_b;
uint8_t reg_msdc1_srcclkena_mask_b;
uint8_t reg_msdc1_infra_req_mask_b;
uint8_t reg_msdc1_apsrc_req_mask_b;
uint8_t reg_msdc1_vrf18_req_mask_b;
uint8_t reg_msdc1_ddren_req_mask_b;
/* SPM_SRC4_MASK */
uint32_t reg_ccif_event_srcclkena_mask_b;
uint8_t reg_bak_psri_srcclkena_mask_b;
uint8_t reg_bak_psri_infra_req_mask_b;
uint8_t reg_bak_psri_apsrc_req_mask_b;
uint8_t reg_bak_psri_vrf18_req_mask_b;
uint8_t reg_bak_psri_ddren_req_mask_b;
uint8_t reg_dramc_md32_infra_req_mask_b;
uint8_t reg_dramc_md32_vrf18_req_mask_b;
uint8_t reg_conn_srcclkenb2pwrap_mask_b;
uint8_t reg_dramc_md32_apsrc_req_mask_b;
/* SPM_SRC5_MASK */
uint32_t reg_mcusys_merge_apsrc_req_mask_b;
uint32_t reg_mcusys_merge_ddren_req_mask_b;
uint8_t reg_afe_srcclkena_mask_b;
uint8_t reg_afe_infra_req_mask_b;
uint8_t reg_afe_apsrc_req_mask_b;
uint8_t reg_afe_vrf18_req_mask_b;
uint8_t reg_afe_ddren_req_mask_b;
uint8_t reg_msdc2_srcclkena_mask_b;
uint8_t reg_msdc2_infra_req_mask_b;
uint8_t reg_msdc2_apsrc_req_mask_b;
uint8_t reg_msdc2_vrf18_req_mask_b;
uint8_t reg_msdc2_ddren_req_mask_b;
/* SPM_WAKEUP_EVENT_MASK */
uint32_t reg_wakeup_event_mask;
/* SPM_WAKEUP_EVENT_EXT_MASK */
uint32_t reg_ext_wakeup_event_mask;
/* SPM_SRC7_MASK */
uint8_t reg_pcie_srcclkena_mask_b;
uint8_t reg_pcie_infra_req_mask_b;
uint8_t reg_pcie_apsrc_req_mask_b;
uint8_t reg_pcie_vrf18_req_mask_b;
uint8_t reg_pcie_ddren_req_mask_b;
uint8_t reg_dpmaif_srcclkena_mask_b;
uint8_t reg_dpmaif_infra_req_mask_b;
uint8_t reg_dpmaif_apsrc_req_mask_b;
uint8_t reg_dpmaif_vrf18_req_mask_b;
uint8_t reg_dpmaif_ddren_req_mask_b;
/* Auto-gen End */
};
check_member(mtk_spm_regs, ap_mdsrc_req, 0x430);
check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0);
check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4);
check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8);
check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC);
struct pcm_desc {
uint32_t pmem_words;
uint32_t total_words;
uint32_t pmem_start;
uint32_t dmem_start;
};
struct dyna_load_pcm {
u8 *buf; /* binary array */
struct pcm_desc desc;
};
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
int spm_init(void);
#endif /* SOC_MEDIATEK_MT8186_SPM_H */

685
src/soc/mediatek/mt8186/spm.c Normal file
View File

@ -0,0 +1,685 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is created based on MT8186 Functional Specification
* Chapter number: 3.5
*/
#include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <soc/mcu_common.h>
#include <soc/spm.h>
#include <soc/spm_common.h>
#include <soc/symbols.h>
#include <string.h>
#include <timer.h>
#define SPM_SYSTEM_BASE_OFFSET 0x40000000
static const struct pwr_ctrl spm_init_ctrl = {
/* For SPM, this flag is not auto-gen. */
.pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS |
SPM_FLAG_DISABLE_VCORE_DFS |
SPM_FLAG_RUN_COMMON_SCENARIO,
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
.reg_wfi_op = 0,
.reg_wfi_type = 0,
.reg_mp0_cputop_idle_mask = 0,
.reg_mp1_cputop_idle_mask = 0,
.reg_mcusys_idle_mask = 0,
.reg_md_apsrc_1_sel = 0,
.reg_md_apsrc_0_sel = 0,
.reg_conn_apsrc_sel = 0,
/* SPM_SRC6_MASK */
.reg_ccif_event_infra_req_mask_b = 0xFFFF,
.reg_ccif_event_apsrc_req_mask_b = 0xFFFF,
/* SPM_SRC_REQ */
.reg_spm_apsrc_req = 0,
.reg_spm_f26m_req = 0,
.reg_spm_infra_req = 0,
.reg_spm_vrf18_req = 0,
.reg_spm_ddren_req = 0,
.reg_spm_dvfs_req = 0,
.reg_spm_sw_mailbox_req = 0,
.reg_spm_sspm_mailbox_req = 0,
.reg_spm_adsp_mailbox_req = 0,
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
.reg_md_0_srcclkena_mask_b = 1,
.reg_md_0_infra_req_mask_b = 1,
.reg_md_0_apsrc_req_mask_b = 1,
.reg_md_0_vrf18_req_mask_b = 1,
.reg_md_0_ddren_req_mask_b = 1,
.reg_md_1_srcclkena_mask_b = 0,
.reg_md_1_infra_req_mask_b = 0,
.reg_md_1_apsrc_req_mask_b = 0,
.reg_md_1_vrf18_req_mask_b = 0,
.reg_md_1_ddren_req_mask_b = 0,
.reg_conn_srcclkena_mask_b = 1,
.reg_conn_srcclkenb_mask_b = 0,
.reg_conn_infra_req_mask_b = 1,
.reg_conn_apsrc_req_mask_b = 1,
.reg_conn_vrf18_req_mask_b = 1,
.reg_conn_ddren_req_mask_b = 1,
.reg_conn_vfe28_mask_b = 0,
.reg_srcclkeni_srcclkena_mask_b = 1,
.reg_srcclkeni_infra_req_mask_b = 1,
.reg_infrasys_apsrc_req_mask_b = 0,
.reg_infrasys_ddren_req_mask_b = 1,
.reg_sspm_srcclkena_mask_b = 1,
.reg_sspm_infra_req_mask_b = 1,
.reg_sspm_apsrc_req_mask_b = 1,
.reg_sspm_vrf18_req_mask_b = 1,
.reg_sspm_ddren_req_mask_b = 1,
/* SPM_SRC2_MASK */
.reg_scp_srcclkena_mask_b = 1,
.reg_scp_infra_req_mask_b = 1,
.reg_scp_apsrc_req_mask_b = 1,
.reg_scp_vrf18_req_mask_b = 1,
.reg_scp_ddren_req_mask_b = 1,
.reg_audio_dsp_srcclkena_mask_b = 1,
.reg_audio_dsp_infra_req_mask_b = 1,
.reg_audio_dsp_apsrc_req_mask_b = 1,
.reg_audio_dsp_vrf18_req_mask_b = 1,
.reg_audio_dsp_ddren_req_mask_b = 1,
.reg_ufs_srcclkena_mask_b = 1,
.reg_ufs_infra_req_mask_b = 1,
.reg_ufs_apsrc_req_mask_b = 1,
.reg_ufs_vrf18_req_mask_b = 1,
.reg_ufs_ddren_req_mask_b = 1,
.reg_disp0_apsrc_req_mask_b = 1,
.reg_disp0_ddren_req_mask_b = 1,
.reg_disp1_apsrc_req_mask_b = 1,
.reg_disp1_ddren_req_mask_b = 1,
.reg_gce_infra_req_mask_b = 1,
.reg_gce_apsrc_req_mask_b = 1,
.reg_gce_vrf18_req_mask_b = 1,
.reg_gce_ddren_req_mask_b = 1,
.reg_apu_srcclkena_mask_b = 0,
.reg_apu_infra_req_mask_b = 0,
.reg_apu_apsrc_req_mask_b = 0,
.reg_apu_vrf18_req_mask_b = 0,
.reg_apu_ddren_req_mask_b = 0,
.reg_cg_check_srcclkena_mask_b = 0,
.reg_cg_check_apsrc_req_mask_b = 0,
.reg_cg_check_vrf18_req_mask_b = 0,
.reg_cg_check_ddren_req_mask_b = 0,
/* SPM_SRC3_MASK */
.reg_dvfsrc_event_trigger_mask_b = 1,
.reg_sw2spm_wakeup_mask_b = 0,
.reg_adsp2spm_wakeup_mask_b = 0,
.reg_sspm2spm_wakeup_mask_b = 0,
.reg_scp2spm_wakeup_mask_b = 0,
.reg_csyspwrup_ack_mask = 1,
.reg_spm_reserved_srcclkena_mask_b = 0,
.reg_spm_reserved_infra_req_mask_b = 0,
.reg_spm_reserved_apsrc_req_mask_b = 0,
.reg_spm_reserved_vrf18_req_mask_b = 0,
.reg_spm_reserved_ddren_req_mask_b = 0,
.reg_mcupm_srcclkena_mask_b = 1,
.reg_mcupm_infra_req_mask_b = 1,
.reg_mcupm_apsrc_req_mask_b = 1,
.reg_mcupm_vrf18_req_mask_b = 1,
.reg_mcupm_ddren_req_mask_b = 1,
.reg_msdc0_srcclkena_mask_b = 1,
.reg_msdc0_infra_req_mask_b = 1,
.reg_msdc0_apsrc_req_mask_b = 1,
.reg_msdc0_vrf18_req_mask_b = 1,
.reg_msdc0_ddren_req_mask_b = 1,
.reg_msdc1_srcclkena_mask_b = 1,
.reg_msdc1_infra_req_mask_b = 1,
.reg_msdc1_apsrc_req_mask_b = 1,
.reg_msdc1_vrf18_req_mask_b = 1,
.reg_msdc1_ddren_req_mask_b = 1,
/* SPM_SRC4_MASK */
.reg_ccif_event_srcclkena_mask_b = 0x3FF,
.reg_bak_psri_srcclkena_mask_b = 0,
.reg_bak_psri_infra_req_mask_b = 0,
.reg_bak_psri_apsrc_req_mask_b = 0,
.reg_bak_psri_vrf18_req_mask_b = 0,
.reg_bak_psri_ddren_req_mask_b = 0,
.reg_dramc_md32_infra_req_mask_b = 1,
.reg_dramc_md32_vrf18_req_mask_b = 0,
.reg_conn_srcclkenb2pwrap_mask_b = 0,
.reg_dramc_md32_apsrc_req_mask_b = 0,
/* SPM_SRC5_MASK */
.reg_mcusys_merge_apsrc_req_mask_b = 0x14,
.reg_mcusys_merge_ddren_req_mask_b = 0x14,
.reg_afe_srcclkena_mask_b = 0,
.reg_afe_infra_req_mask_b = 0,
.reg_afe_apsrc_req_mask_b = 0,
.reg_afe_vrf18_req_mask_b = 0,
.reg_afe_ddren_req_mask_b = 0,
.reg_msdc2_srcclkena_mask_b = 0,
.reg_msdc2_infra_req_mask_b = 0,
.reg_msdc2_apsrc_req_mask_b = 0,
.reg_msdc2_vrf18_req_mask_b = 0,
.reg_msdc2_ddren_req_mask_b = 0,
/* SPM_WAKEUP_EVENT_MASK */
.reg_wakeup_event_mask = 0xEFFFFFFF,
/* SPM_WAKEUP_EVENT_EXT_MASK */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
/* SPM_SRC7_MASK */
.reg_pcie_srcclkena_mask_b = 0,
.reg_pcie_infra_req_mask_b = 0,
.reg_pcie_apsrc_req_mask_b = 0,
.reg_pcie_vrf18_req_mask_b = 0,
.reg_pcie_ddren_req_mask_b = 0,
.reg_dpmaif_srcclkena_mask_b = 1,
.reg_dpmaif_infra_req_mask_b = 1,
.reg_dpmaif_apsrc_req_mask_b = 1,
.reg_dpmaif_vrf18_req_mask_b = 1,
.reg_dpmaif_ddren_req_mask_b = 1,
/* Auto-gen End */
};
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{
/* Auto-gen Start */
/* SPM_AP_STANDBY_CON */
write32(&mtk_spm->spm_ap_standby_con,
((pwrctrl->reg_wfi_op & 0x1) << 0) |
((pwrctrl->reg_wfi_type & 0x1) << 1) |
((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
/* SPM_SRC6_MASK */
write32(&mtk_spm->spm_src6_mask,
((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |
((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));
/* SPM_SRC_REQ */
write32(&mtk_spm->spm_src_req,
((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |
((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
/* SPM_SRC_MASK */
write32(&mtk_spm->spm_src_mask,
((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |
((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
/* SPM_SRC2_MASK */
write32(&mtk_spm->spm_src2_mask,
((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |
((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |
((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |
((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |
((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |
((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));
/* SPM_SRC3_MASK */
write32(&mtk_spm->spm_src3_mask,
((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |
((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |
((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |
((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |
((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |
((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |
((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |
((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |
((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |
((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |
((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));
/* SPM_SRC4_MASK */
write32(&mtk_spm->spm_src4_mask,
((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |
((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |
((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |
((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));
/* SPM_SRC5_MASK */
write32(&mtk_spm->spm_src5_mask,
((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |
((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |
((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |
((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |
((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |
((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |
((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |
((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |
((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |
((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |
((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));
/* SPM_WAKEUP_EVENT_MASK */
write32(&mtk_spm->spm_wakeup_event_mask,
((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
/* SPM_WAKEUP_EVENT_EXT_MASK */
write32(&mtk_spm->spm_wakeup_event_ext_mask,
((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
/* SPM_SRC7_MASK */
write32(&mtk_spm->spm_src7_mask,
((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |
((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |
((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |
((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |
((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |
((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |
((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |
((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |
((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |
((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));
/* Auto-gen End */
}
static void spm_hw_s1_state_monitor(int en)
{
if (en)
SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3,
SPM_ACK_CHK_3_CON_CLR_ALL, 0,
SPM_ACK_CHK_3_CON_EN_0, 1,
SPM_ACK_CHK_3_CON_EN_1, 1);
else
SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3,
SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 1,
SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 1,
SPM_ACK_CHK_3_CON_CLR_ALL, 1,
SPM_ACK_CHK_3_CON_EN_0, 0,
SPM_ACK_CHK_3_CON_EN_1, 0);
}
static void spm_register_init(void)
{
/* Enable register control */
write32(&mtk_spm->poweron_config_en,
SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
/* Init power control register */
write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* Reset PCM */
write32(&mtk_spm->pcm_con0,
SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
write32(&mtk_spm->pcm_con1,
SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB |
REG_MD32_APB_INTERNAL_EN_LSB);
/* Initial SPM CLK control register */
SET32_BITFIELDS(&mtk_spm->spm_clk_con,
REG_SYSCLK1_SRC_MD2_SRCCLKENA, 1);
/* Clean wakeup event raw status */
write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
/* Clean ISR status */
write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
/* Init r7 with POWER_ON_VAL1 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val1));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* DDR EN de-bounce length to 5us */
write32(&mtk_spm->ddren_dbc_con, DDREN_DBC_EN_VAL | REG_DDREN_DBC_EN_LSB);
/* Configure ARMPLL Control Mode for MCDI */
write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF);
/* Init for SPM Resource ACK */
write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF);
write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF);
write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF);
write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF);
/* Enable Side-Band */
write32((void *)AP_PLL_CON3, APMIX_CON3_DEF);
write32((void *)AP_PLL_CON4, APMIX_CON4_DEF);
write32((void *)CLK_SCP_CFG_0, SCP_CFG0_DEF);
write32((void *)CLK_SCP_CFG_1, SCP_CFG1_DEF);
/* Init VCORE DVFS Status */
SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
SPM_DVFS_FORCE_ENABLE_LSB, 0,
SPM_DVFSRC_ENABLE_LSB, 1);
write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1);
write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT);
spm_hw_s1_state_monitor(0);
}
static void spm_extern_initialize(void)
{
SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1,
INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1);
}
static void spm_set_sysclk_settle(void)
{
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
}
static void spm_code_swapping(void)
{
u32 mask;
mask = read32(&mtk_spm->spm_wakeup_event_mask);
write32(&mtk_spm->spm_wakeup_event_mask,
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
write32(&mtk_spm->spm_wakeup_event_mask, mask);
}
static void spm_reset_and_init_pcm(void)
{
bool first_load_fw = true;
/* Check whether the SPM FW is running */
if (read32((void *)MD32PCM_CFGREG_SW_RSTN) & MD32PCM_CFGREG_SW_RSTN_RUN)
first_load_fw = false;
if (!first_load_fw) {
spm_code_swapping();
/* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */
write32(&mtk_spm->spm_power_on_val0,
read32(&mtk_spm->pcm_reg0_data));
}
/* Disable r0 and r7 to control power */
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* Disable pcm timer after leaving FW */
clrsetbits32(&mtk_spm->pcm_con1,
RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
/* Reset PCM */
write32(&mtk_spm->pcm_con0,
SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
/* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB,
SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB);
}
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
{
uintptr_t ptr;
u32 dmem_words;
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
pmem_words = pcm->desc.pmem_words;
total_words = pcm->desc.total_words;
dmem_words = total_words - pmem_words;
pmem_start = pcm->desc.pmem_start;
dmem_start = pcm->desc.dmem_start;
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
__func__, (long)ptr, pmem_words, dmem_words);
/* DMA needs 16-byte aligned source data. */
assert(ptr % 16 == 0);
write32((void *)MD32PCM_DMA0_SRC, ptr);
write32((void *)MD32PCM_DMA0_DST, pmem_start);
write32((void *)MD32PCM_DMA0_WPPT, pmem_words);
write32((void *)MD32PCM_DMA0_WPTO, dmem_start);
write32((void *)MD32PCM_DMA0_COUNT, total_words);
write32((void *)MD32PCM_DMA0_CON, MD32PCM_DMA0_CON_VAL);
write32((void *)MD32PCM_DMA0_START, MD32PCM_DMA0_START_VAL);
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
}
static void spm_init_pcm_register(void)
{
/* Init r0 with POWER_ON_VAL0 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val0));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* Init r7 with POWER_ON_VAL1 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val1));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
write32(&mtk_spm->pcm_pwr_io_en, 0);
}
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
u32 val, mask;
/* Toggle event counter clear */
setbits32(&mtk_spm->pcm_con1,
SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB);
/* Toggle for reset SYS TIMER start point */
SET32_BITFIELDS(&mtk_spm->sys_timer_con,
SYS_TIMER_START_EN_LSB, 1);
if (pwrctrl->timer_val_cust == 0)
val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
else
val = pwrctrl->timer_val_cust;
write32(&mtk_spm->pcm_timer_val, val);
setbits32(&mtk_spm->pcm_con1, RG_PCM_TIMER_EN_LSB | SPM_REGWR_CFG_KEY);
/* Unmask AP wakeup source */
if (pwrctrl->wake_src_cust == 0)
mask = pwrctrl->wake_src;
else
mask = pwrctrl->wake_src_cust;
if (pwrctrl->reg_csyspwrup_ack_mask)
mask &= ~R12_CSYSPWREQ_B;
write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
/* Unmask SPM ISR */
setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX);
/* Toggle event counter clear */
clrsetbits32(&mtk_spm->pcm_con1, REG_SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
/* Toggle for reset SYS TIMER start point */
SET32_BITFIELDS(&mtk_spm->sys_timer_con,
SYS_TIMER_START_EN_LSB, 0);
}
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
{
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
/* Set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0)
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
if (pwrctrl->pcm_flags_cust_set != 0)
pcm_flags |= pwrctrl->pcm_flags_cust_set;
if (pwrctrl->pcm_flags1_cust_clr != 0)
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
if (pwrctrl->pcm_flags1_cust_set != 0)
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
}
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
{
/* Waiting for loading SPMFW done*/
while (read32((void *)MD32PCM_DMA0_RLCT) != 0x0)
;
/* Init register to match PCM expectation */
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
write32(&mtk_spm->spm_bus_protect2_mask_b, SPM_BUS_PROTECT2_MASK_B_DEF);
write32(&mtk_spm->pcm_reg_data_ini, 0);
spm_set_pcm_flags(pwrctrl);
/* Kick PCM to run (only toggle PCM_KICK) */
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
/* Reset md32pcm */
SET32_BITFIELDS((void *)MD32PCM_CFGREG_SW_RSTN,
MD32PCM_CFGREG_SW_RSTN_RESET, 1);
/* Waiting for SPM init done */
udelay(SPM_INIT_DONE_US);
}
static void reset_spm(struct mtk_mcu *mcu)
{
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
spm_parse_firmware(mcu);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcm);
spm_init_pcm_register();
spm_set_power_control(&spm_init_ctrl);
spm_set_wakeup_event(&spm_init_ctrl);
spm_kick_pcm_to_run(&spm_init_ctrl);
}
static struct mtk_mcu spm = {
.firmware_name = CONFIG_SPM_FIRMWARE,
.reset = reset_spm,
};
int spm_init(void)
{
struct dyna_load_pcm pcm;
struct stopwatch sw;
stopwatch_init(&sw);
spm_register_init();
spm_set_power_control(&spm_init_ctrl);
spm_set_sysclk_settle();
spm_extern_initialize();
spm.load_buffer = _dram_dma;
spm.buffer_size = REGION_SIZE(dram_dma);
spm.priv = (void *)&pcm;
if (mtk_init_mcu(&spm)) {
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
return -1;
}
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
__func__, stopwatch_duration_msecs(&sw),
read32(&mtk_spm->md32pcm_pc));
return 0;
}