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mb/amd/gardenia: deselect HAVE_PIRQ_TABLE and drop incorrect irq_tables 

This file isn't correct, since the Stoneyridge SoC doesn't have a legacy
PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select
HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this
board.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2022-09-13 22:18:56 +02:00
parent e74da16741
commit badea79500
2 changed files with 0 additions and 87 deletions
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1
src/mainboard/amd/gardenia/Kconfig
View File

@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_AMD_STONEYRIDGE
select AMD_APU_STONEYRIDGE
select AMD_APU_PKG_FP4
select HAVE_PIRQ_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA

86
src/mainboard/amd/gardenia/irq_tables.c
View File

@ -1,86 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <commonlib/bsd/helpers.h>
#include <device/pci_def.h>
#include <string.h>
#include <stdint.h>
#include <arch/pirq_routing.h>
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
u8 slot, u8 rfu)
{
pirq_info->bus = bus;
pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
u32 slot_num;
u8 *v;
u8 sum = 0;
int i;
/* Align the table to be 16 byte aligned. */
addr = ALIGN_UP(addr, 16);
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = 0;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x1002;
pirq->rtr_device = 0x4384;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
/* PCI bridge */
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++;
slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum)
pirq->checksum = sum;
printk(BIOS_INFO, "%s done.\n", __func__);
return (unsigned long)pirq_info;
}