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baytrail: correct NC pin to GPO pin according to BYT platform design guide 

According to BYT platform design guide chap 14.2.2, the NC GPIOs
need to be configured to GPO.

BRANCH=none
BUG=none
TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO

Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591
Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/249060
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9509
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kane Chen 2015-02-12 16:08:42 +08:00 committed by Stefan Reinauer
parent 555f711cd2
commit bae8608435
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/baytrail/include/soc/gpio.h
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@ -322,7 +322,7 @@
#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU
#define GPIO_INPUT_PU GPIO_INPUT_PU_20K #define GPIO_INPUT_PU GPIO_INPUT_PU_20K
#define GPIO_INPUT_PD GPIO_INPUT_PD_20K #define GPIO_INPUT_PD GPIO_INPUT_PD_20K
#define GPIO_NC GPIO_INPUT_PU_20K #define GPIO_NC GPIO_OUT_HIGH
#define GPIO_DEFAULT GPIO_FUNC0 #define GPIO_DEFAULT GPIO_FUNC0
/* 16 DirectIRQs per supported bank */ /* 16 DirectIRQs per supported bank */