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pci1x2x: use devicetree register configuration 

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Sven Schnelle 2011-04-20 08:57:53 +00:00
parent b297b4901a
commit baec0346b0
4 changed files with 52 additions and 52 deletions
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25
src/mainboard/nokia/ip530/Kconfig
View File

@ -45,29 +45,4 @@ config IRQ_SLOT_COUNT
int
default 22
## Configuration for the PCMCIA-Cardbus controller.
config TI_PCMCIA_CARDBUS_CMDR
hex
default 0x0107
config TI_PCMCIA_CARDBUS_CLSR
hex
default 0x00
config TI_PCMCIA_CARDBUS_CLTR
hex
default 0x40
config TI_PCMCIA_CARDBUS_BCR
hex
default 0x07C0
config TI_PCMCIA_CARDBUS_SCR
hex
default 0x08449060
config TI_PCMCIA_CARDBUS_MRR
hex
default 0x00007522
endif # BOARD_NOKIA_IP530

11
src/mainboard/nokia/ip530/devicetree.cb
View File

@ -28,6 +28,17 @@ chip northbridge/intel/i440bx # Northbridge
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge
device pci f.0 on
chip southbridge/ti/pci1x2x
device pci 00.0 on
end
register "cltr" = "0x40"
register "bcr" = "0x7c0"
register "scr" = "0x08449060"
register "mrr" = "0x00007522"
end
end
device pci 7.0 on # ISA bridge
chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787)
device pnp 3f0.0 off end # Floppy (No connector)

13
src/southbridge/ti/pci1x2x/chip.h Normal file
View File

@ -0,0 +1,13 @@
#ifndef SOUTHBRIDGE_TI_PCI1X2X_H
#define SOUTHBRIDGE_TI_PCI1X2X_H
extern struct chip_operations southbridge_ti_pci1x2x_ops;
struct southbridge_ti_pci1x2x_config {
int scr;
int mrr;
int clsr;
int cltr;
int bcr;
};
#endif

43
src/southbridge/ti/pci1x2x/pci1x2x.c
View File

@ -23,44 +23,41 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \
!defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \
!defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \
!defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \
!defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \
!defined(CONFIG_TI_PCMCIA_CARDBUS_MRR))
#error "you must supply these values in your mainboard-specific Kconfig file"
#endif
#include "chip.h"
static void ti_pci1x2y_init(struct device *dev)
{
printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
/* Command (offset 04) */
pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR);
printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
if (conf) {
/* Cache Line Size (offset 0x0C) */
pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR);
pci_write_config8(dev, 0x0C, conf->clsr);
/* CardBus latency timer (offset 0x1B) */
pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR);
pci_write_config8(dev, 0x1B, conf->cltr);
/* Bridge control (offset 0x3E) */
pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR);
pci_write_config16(dev, 0x3E, conf->bcr);
}
/*
* Enable change sub-vendor ID. Clear the bit 5 to enable to write
* to the sub-vendor/device ids at 40 and 42.
*/
pci_write_config32(dev, 0x80, 0x10);
pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
if (conf) {
/* Now write the correct value for SCR. */
/* System control (offset 0x80) */
pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR);
pci_write_config32(dev, 0x80, conf->scr);
/* Multifunction routing */
pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR);
pci_write_config32(dev, 0x8C, conf->mrr);
}
/* Set the device control register (0x92) accordingly. */
pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
}
static struct device_operations ti_pci1x2y_ops = {
struct device_operations southbridge_ti_pci1x2x_pciops = {
.read_resources = NULL, //pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
@ -69,19 +66,23 @@ static struct device_operations ti_pci1x2y_ops = {
};
static const struct pci_driver ti_pci1225_driver __pci_driver = {
.ops = &ti_pci1x2y_ops,
.ops = &southbridge_ti_pci1x2x_pciops,
.vendor = PCI_VENDOR_ID_TI,
.device = PCI_DEVICE_ID_TI_1225,
};
static const struct pci_driver ti_pci1420_driver __pci_driver = {
.ops = &ti_pci1x2y_ops,
.ops = &southbridge_ti_pci1x2x_pciops,
.vendor = PCI_VENDOR_ID_TI,
.device = PCI_DEVICE_ID_TI_1420,
};
static const struct pci_driver ti_pci1520_driver __pci_driver = {
.ops = &ti_pci1x2y_ops,
.ops = &southbridge_ti_pci1x2x_pciops,
.vendor = PCI_VENDOR_ID_TI,
.device = PCI_DEVICE_ID_TI_1520,
};
struct chip_operations southbridge_ti_pci1x2x_ops = {
CHIP_NAME("TI PCI1x2x Cardbus controller")
};