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mb/google/nissa/var/nivviks: Disable SD card based on fw_config 

BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD
card is enabled/disabled as expected.

Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Reka Norman 2022-05-06 19:55:11 +10:00 committed by Werner Zeh
parent d88233ecd3
commit baf22462b7
2 changed files with 33 additions and 0 deletions
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14
src/mainboard/google/brya/variants/nivviks/fw_config.c
View File

@ -18,11 +18,25 @@ static const struct pad_config lte_disable_pads[] = {
PAD_NC(GPP_H23, NONE),
};
static const struct pad_config sd_disable_pads[] = {
/* D8 : SD_CLKREQ_ODL */
PAD_NC(GPP_D8, NONE),
/* H12 : SD_PERST_L */
PAD_NC(GPP_H12, NONE),
/* H13 : EN_PP3300_SD_X */
PAD_NC(GPP_H13, NONE),
};
static void fw_config_handle(void *unused)
{
if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
}
if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) {
printk(BIOS_INFO, "Disable SD card GPIO pins.\n");
gpio_configure_pads(sd_disable_pads, ARRAY_SIZE(sd_disable_pads));
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

19
src/mainboard/google/brya/variants/nivviks/overridetree.cb
View File

@ -4,6 +4,10 @@ fw_config
option DB_1C_1A 1
option DB_1C_LTE 2
end
field SD_CARD 4
option SD_GL9750S 0
option SD_ABSENT 1
end
end
chip soc/intel/alderlake
@ -231,6 +235,21 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
device ref pcie_rp7 on
# Enable SD Card PCIe 7 using clk 3
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
register "srcclk_pin" = "3"
device generic 0 on end
end
probe SD_CARD SD_GL9750S
end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]