mb/google/nissa/var/nivviks: Disable SD card based on fw_config
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD card is enabled/disabled as expected. Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@ -18,11 +18,25 @@ static const struct pad_config lte_disable_pads[] = {
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PAD_NC(GPP_H23, NONE),
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PAD_NC(GPP_H23, NONE),
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};
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};
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static const struct pad_config sd_disable_pads[] = {
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/* D8 : SD_CLKREQ_ODL */
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PAD_NC(GPP_D8, NONE),
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/* H12 : SD_PERST_L */
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PAD_NC(GPP_H12, NONE),
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/* H13 : EN_PP3300_SD_X */
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PAD_NC(GPP_H13, NONE),
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};
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static void fw_config_handle(void *unused)
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static void fw_config_handle(void *unused)
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{
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{
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if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
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if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
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printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
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printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
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gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
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gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
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}
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}
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if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) {
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printk(BIOS_INFO, "Disable SD card GPIO pins.\n");
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gpio_configure_pads(sd_disable_pads, ARRAY_SIZE(sd_disable_pads));
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}
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@ -4,6 +4,10 @@ fw_config
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option DB_1C_1A 1
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option DB_1C_1A 1
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option DB_1C_LTE 2
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option DB_1C_LTE 2
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end
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end
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field SD_CARD 4
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option SD_GL9750S 0
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option SD_ABSENT 1
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end
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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@ -231,6 +235,21 @@ chip soc/intel/alderlake
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device generic 0 on end
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device generic 0 on end
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end
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end
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end
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end
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device ref pcie_rp7 on
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# Enable SD Card PCIe 7 using clk 3
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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probe SD_CARD SD_GL9750S
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end
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device ref pch_espi on
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device ref pch_espi on
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chip ec/google/chromeec
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn0 as mux_conn[0]
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