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Sklrvp: Update Serial IO modes in devicetree 

This patch updates the Serial IO modes for UART 1 and 2
in devicetree for sklrvp boards.
UART1 is disabled and
UART2 is in PCI mode.

BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for sklrvp and tested LPSS logs on RVP3.

Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da
Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284824
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Naveen Krishna Chatradhi 2015-07-09 17:59:58 +05:30 committed by Patrick Georgi
parent 46ca690ec0
commit baf4e3e92d
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/sklrvp/devicetree.cb
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@ -11,8 +11,8 @@ chip soc/intel/skylake
[PchSerialIoIndexSpi0] = PchSerialIoPci, \
[PchSerialIoIndexSpi1] = PchSerialIoPci, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoPci, \
[PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
# Enable eDP Hotplug with 6ms pulse