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soc/intel/apollolake: Fix overlapping ACPI resource ranges 

The address space allotted to MCRS in the northbridge needs to be exclusive
of the address space allotted to the GPIO controllers in the southbridge,
otherwise Windows complains of overlapping resource ranges and disables
the GPIO controllers. To prevent overlap, use CONFIG_PCR_BASE_ADDRESS
to set the upper bound of MCRS rather than MMCONF.

Test: boot Windows 10/11 on google/{reef,ampton} and verify that
GPIO controllers are indicated as without fault in Device Manager.

Change-Id: I2117054edb448e717b7cbe80958c9c4e6c996e2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
This commit is contained in:
Matt DeVillier 2022-02-13 13:20:36 -06:00 committed by Felix Held
parent 7c31d17317
commit bb052ced54
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/apollolake/acpi/northbridge.asl
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@ -79,8 +79,8 @@ Method (_CRS, 0, Serialized)
/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
PMIN = \_SB.PCI0.MCHC.TLUD & 0xFFF00000 PMIN = \_SB.PCI0.MCHC.TLUD & 0xFFF00000
/* Read MMCONF base */ /* Use PCR base to ensure PMAX below GPIO controllers attached to _SB */
PMAX = \_SB.PCI0.MCHC.MCNF & 0xF0000000 PMAX = CONFIG_PCR_BASE_ADDRESS & 0xF0000000
/* Calculate PCI MMIO Length */ /* Calculate PCI MMIO Length */
PLEN = PMAX - PMIN + 1 PLEN = PMAX - PMIN + 1