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nb/amd/amdmct/mct: Remove commented code 

Change-Id: Id0c62cebfceaf083f1bb39514b06b32c55128b85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17172
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-28 09:56:29 +02:00 committed by Martin Roth
parent ec16e9302b
commit bb09f285c3
6 changed files with 1 additions and 22 deletions
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8
src/northbridge/amd/amdmct/mct/mct_d.c
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@ -1356,7 +1356,6 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
val |= dword;
Set_NB32(dev, reg, val);
}
// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2));
print_tx("AutoCycTiming: Status ", pDCTstat->Status);
print_tx("AutoCycTiming: ErrStatus ", pDCTstat->ErrStatus);
@ -1723,8 +1722,6 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
mct_EarlyArbEn_D(pMCTstat, pDCTstat);
mctHookAfterAutoCfg();
// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2));
print_tx("AutoConfig: Status ", pDCTstat->Status);
print_tx("AutoConfig: ErrStatus ", pDCTstat->ErrStatus);
print_tx("AutoConfig: ErrCode ", pDCTstat->ErrCode);
@ -1858,8 +1855,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
reg = 0x80 + reg_off; /* Bank Addressing Register */
Set_NB32(dev, reg, BankAddrReg);
// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2));
print_tx("SPDSetBanks: Status ", pDCTstat->Status);
print_tx("SPDSetBanks: ErrStatus ", pDCTstat->ErrStatus);
print_tx("SPDSetBanks: ErrCode ", pDCTstat->ErrCode);
@ -2035,8 +2030,6 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
mct_AfterStitchMemory(pMCTstat, pDCTstat, dct);
}
// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2));
print_tx("StitchMemory: Status ", pDCTstat->Status);
print_tx("StitchMemory: ErrStatus ", pDCTstat->ErrStatus);
print_tx("StitchMemory: ErrCode ", pDCTstat->ErrCode);
@ -2399,7 +2392,6 @@ static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i)
u8 *p;
p = pDCTstat->DIMMAddr;
//mct_BeforeGetDIMMAddress();
return p[i];
}

3
src/northbridge/amd/amdmct/mct/mctardk4.c
View File

@ -30,9 +30,6 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
&pDCTstat->_2Tmode);
// print_tx("1 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]);
// print_tx("1 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]);
if (pDCTstat->MAdimms[dct] == 1)
pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */
else

2
src/northbridge/amd/amdmct/mct/mctcsi_d.c
View File

@ -132,8 +132,6 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
print_t("InterleaveBanks_D: Banks Interleaved ");
} /* DoIntlv */
// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2));
print_tx("InterleaveBanks_D: Status ", pDCTstat->Status);
print_tx("InterleaveBanks_D: ErrStatus ", pDCTstat->ErrStatus);
print_tx("InterleaveBanks_D: ErrCode ", pDCTstat->ErrCode);

2
src/northbridge/amd/amdmct/mct/mctdqs_d.c
View File

@ -437,8 +437,6 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
u8 dqsDelay_end;
u8 tmp, valid;
// print_tx("TrainDQSPos: Node_ID", pDCTstat->Node_ID);
// print_tx("TrainDQSPos: Direction", pDCTstat->Direction);
/* MutualCSPassW: each byte represents a bitmap of pass/fail per
* ByteLane. The indext within MutualCSPassW is the delay value

1
src/northbridge/amd/amdmct/mct/mctsrc1p.c
View File

@ -61,7 +61,6 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel,
p[i] = val;
}
// pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel);
return MaxValue;
}

7
src/northbridge/amd/amdmct/mct/mctsrc2p.c
View File

@ -60,12 +60,9 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
u8 bn;
bn = 8;
// print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel);
// print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver);
for (i = 0; i < bn; i++) {
val = p[i];
// print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i);
// print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val);
if (val > max) {
max = val;
}
@ -123,9 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
for (i = 0; i < bn; i++) {
val = p[i];
/* Add 1/2 Memlock delay */
//val += Pass1MemClkDly;
val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES
//val += 0x02;
p[i] = val;
pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
}