baytrail: Add ACPI code to describe GPIO controller

There are 3 banks of GPIOs that need to be described
with specific _UID and memory/interrupt values.

BUG=chrome-os-partner:24314
BRANCH=none
TEST=build and boot on rambi, check for probed driver:

gpiochip_find_base: found new base at 154
gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00
gpiochip_find_base: found new base at 126
gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01
gpiochip_find_base: found new base at 82
gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02

  fed0c000-fed0cfff : INT33FC:00
    fed0c000-fed0cfff : INT33FC:00
  fed0d000-fed0dfff : INT33FC:01
    fed0d000-fed0dfff : INT33FC:01
  fed0e000-fed0efff : INT33FC:02
    fed0e000-fed0efff : INT33FC:02

Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178601
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4985
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

src/soc/intel/baytrail/acpi/gpio.asl

@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <soc/intel/baytrail/baytrail/iomap.h>
+#include <soc/intel/baytrail/baytrail/irq.h>
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+	Name (_HID, "INT33FC")
+	Name (_CID, "INT33FC")
+	Name (_UID, 1)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+		{
+			GPIO_SC_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+		Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+	Name (_HID, "INT33FC")
+	Name (_CID, "INT33FC")
+	Name (_UID, 2)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+		{
+			GPIO_NC_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+		Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+	Name (_HID, "INT33FC")
+	Name (_CID, "INT33FC")
+	Name (_UID, 3)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+		{
+			GPIO_SUS_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+		Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}

src/soc/intel/baytrail/acpi/southcluster.asl

@@ -192,7 +192,6 @@ Device (PDRC)
 		Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
 		Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
 		Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
-		Memory32Fixed(ReadWrite, IO_BASE_ADDRESS, IO_BASE_SIZE)
 		Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
 		Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
 		Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
@@ -233,3 +232,6 @@ Method (_OSC, 4)
 
 // IRQ routing for each PCI device
 #include "irqroute.asl"
+
+// GPIO Devices
+#include "gpio.asl"

src/soc/intel/baytrail/baytrail/gpio.h

@@ -27,9 +27,9 @@
 /* #define GPIO_DEBUG */
 
 /* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */
-#define GPSCORE_PAD_BASE		(IO_BASE_ADDRESS + 0x0000)
+#define GPSCORE_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
-#define GPNCORE_PAD_BASE		(IO_BASE_ADDRESS + 0x1000)
+#define GPNCORE_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE)
-#define GPSSUS_PAD_BASE			(IO_BASE_ADDRESS + 0x2000)
+#define GPSSUS_PAD_BASE		(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
 
 /* DIRQ registers start at pad base + 0x980 */
 #define PAD_BASE_DIRQ_OFFSET		0x980

src/soc/intel/baytrail/baytrail/iomap.h

@@ -39,6 +39,9 @@
 
 /* IO Memory */
 #define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
 #define IO_BASE_SIZE			0x4000
 
 /* Intel Legacy Block */

src/soc/intel/baytrail/baytrail/irq.h

@@ -50,6 +50,9 @@
 #define SCC_EMMC_IRQ			45
 #define SCC_SDIO_IRQ			46
 #define SCC_SD_IRQ			47
+#define GPIO_NC_IRQ			48
+#define GPIO_SC_IRQ			49
+#define GPIO_SUS_IRQ			50
 /* GPIO direct / dedicated IRQs. */
 #define GPIO_S0_DED_IRQ_0		51
 #define GPIO_S0_DED_IRQ_1		52